HC32F460KETA-LQFP64 from XHSC, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PH2	bidirectional	General-purpose I/O on Port H bit 2. Muxed alt functions: EIRQ2, FCMREF, TIM4_2_CLK, TIMA_4_PWM7, EMB_IN4, SDIO2_D4, I2S3_EXCK, EVENTOUT. 5 V tolerant.
2	PC13	bidirectional	GPIO on Port C bit 13. Alt: EIRQ13, RTC_OUT, TIMA_4_PWM8, SDIO2_CK, I2S3_MCK, EVNTP313.
3	PC14/XTAL32_OUT	bidirectional	GPIO Port C bit 14, or 32.768 kHz LSE crystal output XTAL32_OUT. Selected via clock source configuration.
4	PC15/XTAL32_IN	bidirectional	GPIO Port C bit 15, or 32.768 kHz LSE crystal input XTAL32_IN.
5	PH0/XTAL_IN	bidirectional	GPIO Port H bit 0, or main HSE crystal input XTAL_IN. Alt: EIRQ0, TIMA_5_PWM3.
6	PH1/XTAL_OUT	bidirectional	GPIO Port H bit 1, or main HSE crystal output XTAL_OUT. Alt: EIRQ1, TIMA_5_PWM4.
7	NRST	input	Active-low external reset input. Drive low to reset the MCU; internal pull-up.
8	PC0/ADC12_IN10	bidirectional	GPIO Port C bit 0; muxed 12-bit ADC1/ADC2 channel 10 (ADC12_IN10) and CMP3_INP3. Alt: EIRQ0, TIMA_2_PWM5, SDIO2_D5, EVNTP300.
9	PC1/ADC12_IN11	bidirectional	GPIO Port C bit 1; muxed ADC12_IN11. Alt: EIRQ1, TIMA_2_PWM6, SDIO2_D6, EVNTP301.
10	PC2/ADC1_IN12	bidirectional	GPIO Port C bit 2; muxed ADC1 channel 12. Alt: EIRQ2, TIMA_2_PWM7, EMB_IN3, SDIO2_D7, EVNTP302.
11	PC3/ADC1_IN13	bidirectional	GPIO Port C bit 3; muxed ADC1_IN13 / CMP1_INM2. Alt: EIRQ3, TIMA_2_PWM8, SDIO1_WP, EVNTP303.
12	AVSS/VREFL	power_in	Analog ground for ADC/DAC and low reference (VREFL) input. Connect to solid analog-ground plane; on this package VREFL is bonded to AVSS.
13	AVCC/VREFH	power_in	Analog supply for ADC/DAC and high reference (VREFH) input. Nominally 2.7 V-5.5 V. On this package VREFH is bonded to AVCC.
14	PA0/ADC1_IN0	bidirectional	GPIO Port A bit 0; muxed ADC1_IN0 / CMP1_INP1. Alt: EIRQ0/WKUP0_0, TIM4_2_OUH, TIMA_2_PWM1/CLKA, TIMA_2_TRIG, SPI1_SS1, SDIO2_D4, EVNTP100.
15	PA1/ADC1_IN1	bidirectional	GPIO Port A bit 1; muxed ADC1_IN1 / CMP1_INP2. Alt: EIRQ1, TIM4_2_OUL, TIMA_2_PWM2/CLKB, TIMA_3_TRIG, SPI1_SS2, SDIO2_D5, EVNTP101.
16	PA2/ADC1_IN2	bidirectional	GPIO Port A bit 2; muxed ADC1_IN2 / CMP1_INP3. Alt: EIRQ2, TIM4_2_OVH, TIMA_2_PWM3, TIMA_5_PWM1/CLKA, SPI1_SS3, SDIO2_D6, EVNTP102.
17	PA3/ADC1_IN3	bidirectional	GPIO Port A bit 3; muxed ADC1_IN3 / PGAVSS / CMP1_INP4. Alt: EIRQ3, TIM4_2_OVL, TIMA_2_PWM4, TIMA_5_PWM2/CLKB, SDIO2_D7, EVNTP103.
18	AVSS	power_in	Analog ground return for the second analog domain (separate AVSS bond on 64/100-pin packages). Tie to AVSS/VREFL through the analog ground plane.
19	AVCC	power_in	Analog supply for the second analog domain. Tie to AVCC/VREFH; nominally 2.7 V-5.5 V.
20	PA4/ADC12_IN4	bidirectional	GPIO Port A bit 4; muxed ADC12_IN4 / CMP2_INP1 / CMP3_INP4. Alt: EIRQ4, TIM4_2_OWH, TIMA_3_PWM5, USART2_CK, KEYOUT0, I2S1_EXCK, EVNTP104.
21	PA5/ADC12_IN5	bidirectional	GPIO Port A bit 5; muxed ADC12_IN5 / CMP2_INP2. Alt: EIRQ5, TIM4_2_OWL, TIMA_2_PWM1/CLKA, TIMA_3_PWM6, TIMA_2_TRIG, KEYOUT1, I2S1_MCK, EVNTP105.
22	PA6/ADC12_IN6	bidirectional	GPIO Port A bit 6; muxed ADC12_IN6 / CMP2_INP3. Alt: EIRQ6, TIMA_3_PWM1/CLKA, TIMA_3_PWM6, EMB_IN2, KEYOUT2, SDIO1_CMD, EVNTP106.
23	PA7/ADC12_IN7	bidirectional	GPIO Port A bit 7; muxed ADC12_IN7 / CMP1_INM1 / CMP2_INM1 / CMP3_INM1. Alt: EIRQ7, TIM4_1_OUL, TIM6_1_PWMB, TIMA_1_PWM5, TIMA_3_PWM2/CLKB, EMB_IN3, KEYOUT3, SDIO2_WP, EVNTP107.
24	PC4/ADC1_IN14	bidirectional	GPIO Port C bit 4; muxed ADC1_IN14 / CMP2_INM2. Alt: EIRQ4, TIM4_2_OUH, TIMA_3_PWM7, USART1_CK, SDIO2_CD, EVNTP304.
25	PC5/ADC1_IN15	bidirectional	GPIO Port C bit 5; muxed ADC1_IN15 / CMP3_INM2. Alt: EIRQ5, TIM4_2_OUL, TIMA_3_PWM8, SDIO2_CMD, EVNTP305.
26	PB0/ADC12_IN8	bidirectional	GPIO Port B bit 0; muxed ADC12_IN8 / CMP3_INP1. Alt: EIRQ0, TIM4_1_OVL, TIM6_2_PWMB, TIMA_1_PWM6, TIMA_3_PWM3, USART4_CK, KEYOUT4, SDIO2_CMD, EVNTP200.
27	PB1/ADC12_IN9	bidirectional	GPIO Port B bit 1; muxed ADC12_IN9 / CMP3_INP2. Alt: EIRQ1/WKUP0_1, TIM4_1_OWL, TIM6_3_PWMB, TIMA_1_PWM7, TIMA_3_PWM4, QSPI_QSSN, KEYOUT5, SDIO2_D3, I2S2_EXCK, EVNTP201.
28	PB2/PVD2EXINP	bidirectional	GPIO Port B bit 2; muxed programmable-voltage-detector external input PVD2EXINP. Alt: EIRQ2/WKUP0_2, VCOUT123, TIM6_TRIGB, TIMA_1_PWM8, EMB_IN1, QSPI_QSIO3, SDIO2_D2, I2S2_MCK, EVNTP202.
29	PB10	bidirectional	GPIO Port B bit 10. Alt: EIRQ10, ADTRG2, TIM4_2_OVH, TIMA_2_PWM3, TIMA_5_PWM8, QSPI_QSIO2, SDIO1_D7, I2S3_EXCK, EVNTP210.
30	VCAP_1	passive	Internal LDO decoupling / regulator output. Bypass to VSS with a low-ESR ceramic capacitor (typically 2.2 uF - 4.7 uF per reference schematic). Do NOT drive externally.
31	VSS	power_in	Digital ground return. Connect all VSS pins to a solid ground plane.
32	VCC	power_in	Digital supply, 2.7 V-5.5 V (see recommended operating conditions). Decouple with 100 nF close to the pin.
33	PB12	bidirectional	GPIO Port B bit 12. Alt: EIRQ12, VCOUT1, TIM4_2_OVL, TIM6_TRIGB, TIMA_1_PWM8, EMB_IN2, QSPI_QSIO1, SDIO2_D1, I2S3_MCK, EVNTP212.
34	PB13	bidirectional	GPIO Port B bit 13. Alt: EIRQ13, VCOUT2, TIM4_1_OUL, TIM6_1_PWMB, TIMA_1_PWM5, QSPI_QSIO0, SDIO2_D0, EVNTP213.
35	PB14	bidirectional	GPIO Port B bit 14. Alt: EIRQ14, VCOUT3, TIM4_1_OVL, TIM6_2_PWMB, TIMA_1_PWM6, QSPI_QSCK, SDIO1_D6, EVNTP214.
36	PB15	bidirectional	GPIO Port B bit 15. Alt: EIRQ15, RTC_OUT, TIM4_1_OWL, TIM6_3_PWMB, TIMA_1_PWM7, TIMA_6_TRIG, EMB_IN4, USART3_CK, SDIO1_CK, EVNTP215.
37	PC6	bidirectional	GPIO Port C bit 6. Alt: EIRQ6, TIMA_3_PWM1/CLKA, TIMA_5_PWM8, QSPI_QSCK, KEYOUT3, SDIO1_D6, EVNTP306.
38	PC7	bidirectional	GPIO Port C bit 7. Alt: EIRQ7, TIM4_2_CLK, TIMA_3_PWM2/CLKB, TIMA_5_PWM7, QSPI_QSSN, KEYOUT2, SDIO1_D7, I2S2_EXCK, EVNTP307.
39	PC8	bidirectional	GPIO Port C bit 8. Alt: EIRQ8, TIM4_2_OWH, TIMA_3_PWM3, TIMA_5_PWM6, USART3_CK, KEYOUT1, SDIO1_D0, I2S2_MCK, EVNTP308.
40	PC9	bidirectional	GPIO Port C bit 9. Alt: EIRQ9, MCO_2, TIM4_2_OWL, TIMA_3_PWM4, TIMA_5_PWM5, KEYOUT0, SDIO1_D1, EVNTP309.
41	PA8	bidirectional	GPIO Port A bit 8. Alt: EIRQ8/WKUP2_0, MCO_1, TIM4_1_OUH, TIM6_1_PWMA, TIMA_1_PWM1/CLKA, USART1_CK, SDIO1_D1, USBFS_SOF, EVNTP108.
42	PA9/USBFS_VBUS	bidirectional	GPIO Port A bit 9 or USB 2.0 Full-Speed VBUS sense input. Alt: EIRQ9/WKUP2_1, TIM4_1_OVH, TIM6_2_PWMA, TIMA_1_PWM2/CLKB, SDIO1_D2, EVNTP109.
43	PA10/USBFS_ID	bidirectional	GPIO Port A bit 10 or USB OTG identifier pin USBFS_ID. Alt: EIRQ10/WKUP2_2, TIM4_1_OWH, TIM6_3_PWMA, TIMA_1_PWM3, TIMA_5_TRIG, SDIO1_CD, EVNTP110.
44	PA11/USBFS_DM	bidirectional	GPIO Port A bit 11 or USB 2.0 FS D- line. Alt: EIRQ11/WKUP2_3, TIM4_1_CLK, TIMA_1_PWM4, EMB_IN1, SDIO2_CD, EVNTP111. Not 5 V tolerant.
45	PA12/USBFS_DP	bidirectional	GPIO Port A bit 12 or USB 2.0 FS D+ line. Alt: EIRQ12/WKUP3_0, TIM4_3_OWL, TIM6_TRIGA, TIMA_1_TRIG, TIMA_6_PWM1/CLKA, SDIO2_WP, EVNTP112. Not 5 V tolerant.
46	PA13/JTMS_SWDIO	bidirectional	GPIO Port A bit 13; default JTAG mode-select / SWD data (JTMS/SWDIO). Alt: EIRQ13/WKUP3_1, TIMA_2_PWM5, TIMA_6_PWM2/CLKB, SPI2_SS1, SDIO2_D3, EVNTP113.
47	VSS	power_in	Digital ground return.
48	VCC	power_in	Digital supply, 2.7 V-5.5 V. Decouple with 100 nF close to the pin.
49	PA14/JTCK_SWCLK	bidirectional	GPIO Port A bit 14; default JTAG clock / SWD clock (JTCK/SWCLK). Alt: EIRQ14/WKUP3_2, TIMA_2_PWM6, TIMA_6_PWM3, TIMA_4_TRIG, SPI2_SS2, SDIO2_D2, I2S1_EXCK, EVNTP114.
50	PA15/JTDI	bidirectional	GPIO Port A bit 15; default JTAG data input (JTDI). Alt: EIRQ15/WKUP3_3, TIMA_2_PWM1/CLKA, TIMA_6_PWM4, TIMA_2_TRIG, SPI2_SS3, SDIO2_D1, I2S1_MCK, EVNTP115.
51	PC10	bidirectional	GPIO Port C bit 10. Alt: EIRQ10, TIM4_3_OUH, TIMA_2_PWM7, TIMA_5_PWM1/CLKA, SDIO1_D2, EVNTP310.
52	PC11	bidirectional	GPIO Port C bit 11. Alt: EIRQ11, TIM4_3_OVH, TIMA_2_PWM8, TIMA_5_PWM2/CLKB, SDIO1_D3, EVNTP311.
53	PC12	bidirectional	GPIO Port C bit 12. Alt: EIRQ12, TIM4_3_OWH, TIMA_4_TRIG, TIMA_5_PWM3, SDIO1_CK, EVNTP312.
54	PD2	bidirectional	GPIO Port D bit 2 (only bit of Port D bonded on LQFP-64). Alt: EIRQ2, TIMA_2_PWM4, TIMA_6_PWM6, SDIO1_CMD, EVNTP402.
55	PB3/JTDO_TRACESWO	bidirectional	GPIO Port B bit 3; default JTAG data out / SW trace output (JTDO/TRACESWO). Alt: EIRQ3/WKUP0_3, FCMREF, TIM4_3_CLK, TIMA_2_PWM2/CLKB, TIMA_6_PWM5, SDIO2_D0, EVNTP203.
56	PB4/NJTRST	bidirectional	GPIO Port B bit 4; default JTAG active-low reset (NJTRST). Alt: EIRQ4/WKUP1_0, TIM4_3_OWL, TIMA_3_PWM1/CLKA, TIMA_6_PWM6, SDIO1_D0, EVNTP204.
57	PB5	bidirectional	GPIO Port B bit 5. Alt: EIRQ5/WKUP1_1, TIM4_3_OWH, TIMA_3_PWM2/CLKB, TIMA_6_PWM7, SDIO1_D3, I2S4_EXCK, EVNTP205.
58	PB6	bidirectional	GPIO Port B bit 6. Alt: EIRQ6/WKUP1_2, ADTRG2, TIM4_3_OVL, TIMA_4_PWM1/CLKA, TIMA_6_PWM8, SDIO2_CK, I2S4_MCK, EVNTP206.
59	PB7	bidirectional	GPIO Port B bit 7. Alt: EIRQ7/WKUP1_3, ADTRG1, TIM4_3_OVH, TIMA_4_PWM2/CLKB, SDIO1_D0, EVNTP207.
60	PB11/MD	input	Input-only pin (Port B bit 11). Doubles as non-maskable interrupt (NMI) and mode-selection input MD. No output driver per Table 2-4.
61	PB8	bidirectional	GPIO Port B bit 8. Alt: EIRQ8, TIM4_3_OUL, TIMA_4_PWM3, KEYOUT7, SDIO1_D4, USBFS_DRVVBUS, EVNTP208.
62	PB9	bidirectional	GPIO Port B bit 9. Alt: EIRQ9, TIM4_3_OUH, TIMA_4_PWM4, TIMA_6_TRIG, SPI2_SS1, KEYOUT6, SDIO1_D5, EVNTP209.
63	VSS	power_in	Digital ground return.
64	VCC	power_in	Digital supply, 2.7 V-5.5 V. Decouple with 100 nF close to the pin.

Key specifications

Parameter	Value
Manufacturer	XHSC
Package	LQFP-64(10x10)
Category	MCU
Pins	64

Ordering variants

Same part, different packaging or reel option.

HC32F460KETA-LQFP64
HC32F460KCTA-LQFP64
HC32F460KEUA-QFN60TR
HC32F460PETB-LQFP100
HC32F460PCTB-LQFP100
HC32F460PEHB-VFBGA100
HC32F460JETA-LQFP48
HC32F460JCTA-LQFP48
HC32F460JEUA-QFN48TR

CAD (KiCad official)

Symbol: HC32F460KETA-LQFP64
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: XHSC datasheet (116 pp, sha256 df339d0329616ae4, retrieved 2026-08-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF