component

GD25Q64ETIGR

Public Unreviewed

by Ray

GigaDevice Semicon Beijing NOR FLASH, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.

componentmemorygd25q64etigr
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads on click. Unloads when scrolled away or the tab is hidden.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads when scrolled away or the tab is hidden.

PCB Footprint

Open full view ↗
Loads on click. Unloads when scrolled away or the tab is hidden.

Datasheet

Open in new tab ↗
Loads on click. Unloads when scrolled away or the tab is hidden.
Download PDF
Contents

README

markdown

GD25Q64ETIGR

GigaDevice Semicon Beijing · NOR FLASH · SOIC-8

GD25Q64ETIGR from GigaDevice Semicon Beijing, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS# input Chip Select input, active low. Must be driven high when the device is not selected; do not leave floating after power-on. Enables/disables the SPI interface and terminates command sequences on rising edge.
2 SO/IO1 bidirectional Serial Data Output in Standard SPI mode (SO). Becomes bidirectional I/O line IO1 in Dual/Quad SPI modes.
3 WP#/IO2 bidirectional Active-low Write Protect input in Standard/Dual SPI: hardware-protects the Status Register BP4-BP0 and SRP bits when low. Becomes bidirectional I/O line IO2 when Quad SPI is enabled (QE=1 in Status Register).
4 VSS power_in Ground reference for the device (0 V).
5 SI/IO0 bidirectional Serial Data Input in Standard SPI mode (SI). Becomes bidirectional I/O line IO0 in Dual/Quad SPI modes. Data on SI is latched on the rising edge of SCLK.
6 SCLK input Serial Clock input. Provides the timing reference for the serial interface; input data is latched on the rising edge and output data shifts on the falling edge. SPI modes 0 and 3 are supported, up to 133 MHz.
7 HOLD#/IO3 bidirectional Active-low Hold input in Standard/Dual SPI: pausing serial communication without deselecting the device (SO goes hi-Z; SI and SCLK are don't-care during hold). Becomes bidirectional I/O line IO3 when Quad SPI is enabled (QE=1). HOLD function is disabled when QE=1.
8 VCC power_in Single power supply input, full voltage range 2.7 V to 3.6 V. Should be bypassed to VSS with a decoupling capacitor close to the pin.

Key specifications

Parameter Value
Manufacturer GigaDevice Semicon Beijing
Package SOIC-8
Category Memory
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • GD25Q64ETIGR
  • GD25Q64ETIGT
  • GD25Q64ETIGY
  • GD25Q64ETIGRETISR
  • GD25Q64ETIGRETIST
  • GD25Q64ETIGRETISY
  • GD25Q64ETIGRETJG*
  • GD25Q64ETIGRETJS*
  • GD25Q64ETIGRETEG*
  • GD25Q64ETIGRETES*
  • GD25Q64ETIGRETFG*
  • GD25Q64ETIGRETFS*
  • GD25Q64ETIGRESIG
  • GD25Q64ETIGRESIS
  • GD25Q64ETIGRESJG
  • GD25Q64ETIGRESJS
  • GD25Q64ETIGRESEG
  • GD25Q64ETIGRESES
  • GD25Q64ETIGRESFG
  • GD25Q64ETIGRESFS
  • GD25Q64ETIGREFIG
  • GD25Q64ETIGREFIS
  • GD25Q64ETIGREFJG
  • GD25Q64ETIGREFJS
  • GD25Q64ETIGREFEG
  • GD25Q64ETIGREFES
  • GD25Q64ETIGREFFG
  • GD25Q64ETIGREFFS
  • GD25Q64ETIGRENIG
  • GD25Q64ETIGRENIS
  • GD25Q64ETIGRENJG
  • GD25Q64ETIGRENJS
  • GD25Q64ETIGRENEG
  • GD25Q64ETIGRENES
  • GD25Q64ETIGRENFG
  • GD25Q64ETIGRENFS
  • GD25Q64ETIGREQIG
  • GD25Q64ETIGREQIS
  • GD25Q64ETIGREQJG
  • GD25Q64ETIGREQJS
  • GD25Q64ETIGREQEG
  • GD25Q64ETIGREQES
  • GD25Q64ETIGREQFG
  • GD25Q64ETIGREQFS
  • GD25Q64ETIGREWIG
  • GD25Q64ETIGREWIS
  • GD25Q64ETIGREWJG
  • GD25Q64ETIGREWJS
  • GD25Q64ETIGREWEG
  • GD25Q64ETIGREWES
  • GD25Q64ETIGREWFG
  • GD25Q64ETIGREWFS
  • GD25Q64ETIGREYIG
  • GD25Q64ETIGREYIS
  • GD25Q64ETIGREYJG
  • GD25Q64ETIGREYJS
  • GD25Q64ETIGREYEG
  • GD25Q64ETIGREYES
  • GD25Q64ETIGREYFG
  • GD25Q64ETIGREYFS
  • GD25Q64ETIGREZIG
  • GD25Q64ETIGREZIS
  • GD25Q64ETIGREZJG
  • GD25Q64ETIGREZJS
  • GD25Q64ETIGREZEG
  • GD25Q64ETIGREZES
  • GD25Q64ETIGREZFG
  • GD25Q64ETIGREZFS
  • GD25Q64ETIGREBIG
  • GD25Q64ETIGREBIS
  • GD25Q64ETIGREBJG
  • GD25Q64ETIGREBJS
  • GD25Q64ETIGREBEG
  • GD25Q64ETIGREBES
  • GD25Q64ETIGREBFG
  • GD25Q64ETIGREBFS

CAD (KiCad official)

  • Symbol: GD25Q64ETIGR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: GigaDevice Semicon Beijing datasheet (63 pp, sha256 c858ff8e1991d687, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF