FT61F135-TRB from FMD Fremont Micro Devices, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GND	power_in	Ground reference (0 V) for the digital core, I/O and analog supplies.
2	PC1/OSC1/ICSPDAT	bidirectional	Port C bit 1 general-purpose I/O. Alt: OSC1 crystal driver input (LP/XT external clock mode); ICSPDAT in-system programming / OCD serial data.
3	PC0/OSC2/ICSPCLK	bidirectional	Port C bit 0 general-purpose I/O. Alt: OSC2 crystal driver output; ICSPCLK in-system programming / OCD clock input.
4	PB7/[P1B1]/MCLRB	bidirectional	Port B bit 7 GPIO. Alt: P1B1 remapped PWM output; MCLRB active-low external reset input (weak pull-up enabled when configured as MCLR).
5	PB6/ELVD0/[P1A1N]	bidirectional	Port B bit 6 GPIO. Alt: ELVD0 external low-voltage-detect input 0; P1A1N remapped complementary PWM output.
6	PB5/AN7/ELVD1/[P1A1]	bidirectional	Port B bit 5 GPIO. Alt: AN7 ADC analog channel 7; ELVD1 external LVD input 1; P1A1 remapped PWM output.
7	PB4/ATEST0	bidirectional	Port B bit 4 GPIO. Alt: ATEST0 internal test pin (factory use).
8	PB3/P1D0	bidirectional	Port B bit 3 GPIO. Alt: P1D0 PWM D-channel output.
9	PB2/P1C0	bidirectional	Port B bit 2 GPIO. Alt: P1C0 PWM C-channel output.
10	PB1/P1A0N	bidirectional	Port B bit 1 GPIO. Alt: P1A0N complementary output of PWM A channel (dead-time pair with P1A0).
11	PB0/AN6/[P1C1]/CLKO	bidirectional	Port B bit 0 GPIO. Alt: AN6 ADC analog channel 6; P1C1 remapped PWM output; CLKO instruction clock output.
12	PA7/AN5/P1B0/[ICSPDAT1]	bidirectional	Port A bit 7 GPIO with pin-change interrupt. Alt: AN5 ADC analog channel 5; P1B0 PWM B-channel output; ICSPDAT1 remapped ICSP data.
13	PA6/AN4/P1A0/[ICSPCLK1]	bidirectional	Port A bit 6 GPIO with pin-change interrupt. Alt: AN4 ADC analog channel 4; P1A0 PWM A-channel output; ICSPCLK1 remapped ICSP clock input.
14	PA5/VREFN	bidirectional	Port A bit 5 GPIO with pin-change interrupt. Alt: VREFN ADC external negative reference input.
15	PA4/AN3/VREFP/INT/BKIN/ADC_ETR/AT0	bidirectional	Port A bit 4 GPIO with pin-change interrupt. Alt: AN3 ADC channel 3; VREFP ADC positive reference input; INT external interrupt; BKIN PWM brake input; ADC_ETR external ADC trigger; AT0 factory test.
16	PA3/[P1D1]	bidirectional	Port A bit 3 GPIO with pin-change interrupt. Alt: P1D1 remapped PWM D-channel output.
17	PA2/AN2/T0CKI/[CLKO]/[P1D2]	bidirectional	Port A bit 2 GPIO with pin-change interrupt. Alt: AN2 ADC channel 2; T0CKI Timer0 external clock input; CLKO remapped system-clock output; P1D2 remapped PWM output.
18	PA1/AN1/ELVD2/[P1A2]	bidirectional	Port A bit 1 GPIO with pin-change interrupt. Alt: AN1 ADC channel 1; ELVD2 external LVD input 2; P1A2 remapped PWM output.
19	PA0/AN0/ELVD3/[P1A2N]	bidirectional	Port A bit 0 GPIO with pin-change interrupt. Alt: AN0 ADC channel 0; ELVD3 external LVD input 3; P1A2N remapped complementary PWM output.
20	VDD	power_in	Main positive supply, 1.9 V to 5.5 V (>=2.7 V required for 16 MHz operation). Bypass locally with a 100 nF ceramic capacitor.

Key specifications

Parameter	Value
Manufacturer	FMD Fremont Micro Devices
Package	TSSOP-20
Category	MCU
Pins	20

Ordering variants

Same part, different packaging or reel option.

FT61F135-TRB
FT61F135-RB
FT61F135-DRB
FT61F133A-RB
FT61F132A-RB
FT61F13F-MRB
FT61F131B-RB

CAD (KiCad official)

Symbol: FT61F135-TRB
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: FMD Fremont Micro Devices datasheet (143 pp, sha256 1b2826a8737e5853, retrieved 2026-08-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF