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ft61f0a5-trb

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by Ray

FMD Fremont Micro Devices Microcontrollers (MCU/MPU/SOC), TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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FT61F0A5-TRB

FMD Fremont Micro Devices · Microcontrollers (MCU/MPU/SOC) · TSSOP-20

FT61F0A5-TRB from FMD Fremont Micro Devices, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA5/LVDOUT/TIM2_CH1/UART1_CK bidirectional General-purpose I/O PA5. Alternate functions: LVDOUT (LVD level output), TIM2_CH1 PWM channel 1, UART1_CK synchronous-mode clock output. OP0P (op-amp positive input) is not implemented on FT61F0Ax.
2 PA6/AN3/UART1_TX/[AT0] bidirectional General-purpose I/O PA6. Alternates: AN3 ADC channel 3 input, UART1_TX data output, AT0 internal test pin. OP0N not implemented on FT61F0Ax.
3 PA7/AN4/[CLKO]/[TIM1_CH4]/UART1_RX/ELVD0/[AT1] bidirectional General-purpose I/O PA7. Alternates: AN4 ADC channel 4, CLKO internal clock output (remap), TIM1_CH4 PWM channel 4, UART1_RX data input, ELVD0 external LVD detect input 0, AT1 test pin. OP0OUT/UART2_TX not implemented on FT61F0Ax (no op-amp, no UART2).
4 PC0/AN5/MCLRB/TIM1_CH1N/ELVD1 bidirectional General-purpose I/O PC0. Alternates: AN5 ADC channel 5, MCLRB external reset input (active low), TIM1_CH1N complementary PWM channel 1, ELVD1 external LVD input 1.
5 PC1/OSC1/[SPI_MISO]/ELVD2 bidirectional General-purpose I/O PC1. Alternates: OSC1 crystal/resonator input pin 1, SPI_MISO master-in slave-out (remap), ELVD2 external LVD input 2.
6 PB7/OSC2/[SPI_MOSI]/ELVD3 bidirectional General-purpose I/O PB7. Alternates: OSC2 crystal/resonator input pin 2, SPI_MOSI master-out slave-in (remap), ELVD3 external LVD input 3.
7 GND power_in Device ground reference (0 V). All ground currents return here.
8 PB6/AN6/I2C_SDA/[UART1_TX]/ISPDAT bidirectional General-purpose I/O PB6. Alternates: AN6 ADC channel 6, I2C_SDA data line, UART1_TX (remap), ISPDAT in-system-programming data I/O.
9 VDD power_in Main power supply. Operating range 1.9 V to 5.5 V (8 MHz operation requires VDD ≥ 1.9 V; 16 MHz requires VDD ≥ 2.7 V; IAP requires VDD ≥ 2.7 V).
10 PB5/[LVDOUT]/TIM2_CH3/SPI_NSS bidirectional General-purpose I/O PB5. Alternates: LVDOUT LVD level output (remap), TIM2_CH3 PWM channel 3 output, SPI_NSS slave-select. UART2_RX not implemented on FT61F0Ax (no UART2).
11 PB4/[LVDOUT]/I2C_SDA/TIM1_BKIN bidirectional General-purpose I/O PB4. Alternates: LVDOUT (remap), I2C_SDA data line (remap), TIM1_BKIN break input for TIM1 PWM. UART2_TX not implemented on FT61F0Ax.
12 PB3/[LVDOUT]/I2C_SCL/[ADC_ETR]/TIM1_ETR bidirectional General-purpose I/O PB3. Alternates: LVDOUT (remap), I2C_SCL clock line, ADC_ETR external ADC trigger (remap), TIM1_ETR TIM1 external trigger. UART2_CK not implemented on FT61F0Ax.
13 PB2/TIM1_CH3/[SPI_SCK]/[TIM1_CH1N] bidirectional General-purpose I/O PB2. Alternates: TIM1_CH3 PWM channel 3, SPI_SCK clock (remap), TIM1_CH1N complementary PWM channel 1 (remap).
14 PB1/AN0/TIM1_CH4/CLKO/TIM1_CH2N bidirectional General-purpose I/O PB1. Alternates: AN0 ADC channel 0, TIM1_CH4 PWM channel 4 output, CLKO internal clock output, TIM1_CH2N complementary PWM channel 2.
15 PB0/[TIM1_CH2]/SPI_CK/TIM1_CH3N/[TIM2_CH1] bidirectional General-purpose I/O PB0. Alternates: TIM1_CH2 PWM output (remap), SPI_CK clock, TIM1_CH3N complementary PWM channel 3, TIM2_CH1 PWM output (remap).
16 PA0/SPI_MOSI/TIM1_CH1/VREFN bidirectional General-purpose I/O PA0. Alternates: SPI_MOSI master-out slave-in, TIM1_CH1 PWM channel 1, VREFN external ADC negative reference input.
17 PA1/SPI_MISO/TIM1_CH2/VREFP bidirectional General-purpose I/O PA1. Alternates: SPI_MISO master-in slave-out, TIM1_CH2 PWM channel 2, VREFP external ADC positive reference input.
18 PA2/[TIM1_CH4]/[I2C_SCL]/[UART1_RX]/ISPCK bidirectional General-purpose I/O PA2. Alternates: TIM1_CH4 PWM output (remap), I2C_SCL clock (remap), UART1_RX data input (remap), ISPCK in-system-programming clock input.
19 PA3/AN1/[TIM2_CH3] bidirectional General-purpose I/O PA3. Alternates: AN1 ADC channel 1, TIM2_CH3 PWM output (remap). UART2_TX not implemented on FT61F0Ax.
20 PA4/AN2/TIM2_CH2/ADC_ETR bidirectional General-purpose I/O PA4. Alternates: AN2 ADC channel 2, TIM2_CH2 PWM channel 2, ADC_ETR external ADC trigger input. UART2_RX not implemented on FT61F0Ax.

Key specifications

Parameter Value
Manufacturer FMD Fremont Micro Devices
Package TSSOP-20
Category MCU
Pins 20

Ordering variants

  • FT61F0A5-TRB
  • FT61F0A5-TRBA5-RB
  • FT61F0A5-TRBA5-NRT
  • FT61F0A5-TRBA3-RB
  • FT61F0A5-TRBAF-MRB
  • FT61F0A5-TRBA1-RB

CAD (KiCad official)

  • Symbol: FT61F0A5-TRB
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
ft61f0a5-trb.step 267 KB You want the bare part, or you mark your own boards.
ft61f0a5-trb-etched.step 2.7 MB You want the part with FT61F0A5-TRB already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 694 faces against 327 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: FMD Fremont Micro Devices datasheet (282 pp, sha256 a62017cffcbf43ef, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

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PCB Footprint

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