component
ft4232hl-reel
Public Unreviewedby Ray
FTDI USB Converters, LQFP-64(10x10). Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
README
markdownFT4232HL-Reel
FTDI · USB Converters · LQFP-64(10x10)
FT4232HL-Reel from FTDI, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | 0 V digital ground input. |
| 2 | OSCI | input | Oscillator input. Connect the 12 MHz crystal here (or an external 12 MHz reference). |
| 3 | OSCO | output | Oscillator output. Connect the second terminal of the 12 MHz crystal here. |
| 4 | VPHY | power_in | +3.3 V internal USB PHY power supply input. Must not be tied directly to VBUS; supply from a 3.3 V regulator, LC-filtered. |
| 5 | GND | power_in | 0 V digital ground input. |
| 6 | REF | input | Bandgap current reference. Connect to GND via a 12 kΩ 1% resistor. |
| 7 | DM | bidirectional | USB 2.0 data signal minus (D−). Connect to the USB connector D− via appropriate series resistors per USB compliance. |
| 8 | DP | bidirectional | USB 2.0 data signal plus (D+). Connect to the USB connector D+ per USB compliance. |
| 9 | VPLL | power_in | +3.3 V internal PHY PLL power supply input. Filter with an LC network. |
| 10 | AGND | power_in | 0 V analog ground. |
| 11 | GND | power_in | 0 V digital ground input. |
| 12 | VCORE | power_in | +1.8 V core supply input. Tie to VREGOUT (pin 49) with a 3.3 µF filter capacitor. |
| 13 | TEST | input | Factory test pin. Must be tied to GND for normal operation. |
| 14 | RESET# | input | Active-low reset input. Pull high (via pull-up) for normal operation; assert low to reset the device. |
| 15 | GND | power_in | 0 V digital ground input. |
| 16 | ADBUS0 | bidirectional | Channel A bit 0. UART: TXD (output). Async/Sync bit-bang: D0. MPSSE: TCK/SK clock output. |
| 17 | ADBUS1 | bidirectional | Channel A bit 1. UART: RXD (input). Bit-bang: D1. MPSSE: TDI/DO output. |
| 18 | ADBUS2 | bidirectional | Channel A bit 2. UART: RTS# (output). Bit-bang: D2. MPSSE: TDO/DI input. |
| 19 | ADBUS3 | bidirectional | Channel A bit 3. UART: CTS# (input). Bit-bang: D3. MPSSE: TMS/CS output. |
| 20 | VCCIO | power_in | +3.3 V I/O interface power supply input. Failure to connect all VCCIO pins will result in device failure. |
| 21 | ADBUS4 | bidirectional | Channel A bit 4. UART: DTR# (output). Bit-bang: D4. MPSSE: GPIOL0. |
| 22 | ADBUS5 | bidirectional | Channel A bit 5. UART: DSR# (input). Bit-bang: D5. MPSSE: GPIOL1. |
| 23 | ADBUS6 | bidirectional | Channel A bit 6. UART: DCD# (input). Bit-bang: D6. MPSSE: GPIOL2. |
| 24 | ADBUS7 | bidirectional | Channel A bit 7. UART: RI# input or TXDEN output (EEPROM-selectable; default RI#). Bit-bang: D7. MPSSE: GPIOL3. |
| 25 | GND | power_in | 0 V digital ground input. |
| 26 | BDBUS0 | bidirectional | Channel B bit 0. UART: TXD (output). Bit-bang: D0. MPSSE: TCK/SK. |
| 27 | BDBUS1 | bidirectional | Channel B bit 1. UART: RXD (input). Bit-bang: D1. MPSSE: TDI/DO. |
| 28 | BDBUS2 | bidirectional | Channel B bit 2. UART: RTS# (output). Bit-bang: D2. MPSSE: TDO/DI. |
| 29 | BDBUS3 | bidirectional | Channel B bit 3. UART: CTS# (input). Bit-bang: D3. MPSSE: TMS/CS. |
| 30 | BDBUS4 | bidirectional | Channel B bit 4. UART: DTR# (output). Bit-bang: D4. MPSSE: GPIOL0. |
| 31 | VCCIO | power_in | +3.3 V I/O interface power supply input. All VCCIO pins must be connected. |
| 32 | BDBUS5 | bidirectional | Channel B bit 5. UART: DSR# (input). Bit-bang: D5. MPSSE: GPIOL1. |
| 33 | BDBUS6 | bidirectional | Channel B bit 6. UART: DCD# (input). Bit-bang: D6. MPSSE: GPIOL2. |
| 34 | BDBUS7 | bidirectional | Channel B bit 7. UART: RI# or TXDEN (EEPROM-selectable). Bit-bang: D7. MPSSE: GPIOL3. |
| 35 | GND | power_in | 0 V digital ground input. |
| 36 | SUSPEND# | output | Active-low output; asserted when USB is in suspend mode. Useful for gating external circuitry when suspended. |
| 37 | VCORE | power_in | +1.8 V core supply input. All VCORE pins must be tied together and to VREGOUT. |
| 38 | CDBUS0 | bidirectional | Channel C bit 0. UART: TXD. Bit-bang: D0. Channel C supports RS232/RS422/RS485 or bit-bang (no MPSSE). |
| 39 | CDBUS1 | bidirectional | Channel C bit 1. UART: RXD. Bit-bang: D1. |
| 40 | CDBUS2 | bidirectional | Channel C bit 2. UART: RTS#. Bit-bang: D2. |
| 41 | CDBUS3 | bidirectional | Channel C bit 3. UART: CTS#. Bit-bang: D3. |
| 42 | VCCIO | power_in | +3.3 V I/O interface power supply input. All VCCIO pins must be connected. |
| 43 | CDBUS4 | bidirectional | Channel C bit 4. UART: DTR#. Bit-bang: D4. |
| 44 | CDBUS5 | bidirectional | Channel C bit 5. UART: DSR#. Bit-bang: D5. |
| 45 | CDBUS6 | bidirectional | Channel C bit 6. UART: DCD#. Bit-bang: D6. |
| 46 | CDBUS7 | bidirectional | Channel C bit 7. UART: RI# or TXDEN (EEPROM-selectable). Bit-bang: D7. |
| 47 | GND | power_in | 0 V digital ground input. |
| 48 | DDBUS0 | bidirectional | Channel D bit 0. UART: TXD. Bit-bang: D0. Channel D supports RS232/RS422/RS485 or bit-bang (no MPSSE). |
| 49 | VREGOUT | power_out | +1.8 V output of the integrated LDO. Connect to all VCORE pins with a 3.3 µF filter capacitor. |
| 50 | VREGIN | power_in | +3.3 V input to the integrated 1.8 V LDO regulator. |
| 51 | GND | power_in | 0 V digital ground input. |
| 52 | DDBUS1 | bidirectional | Channel D bit 1. UART: RXD. Bit-bang: D1. |
| 53 | DDBUS2 | bidirectional | Channel D bit 2. UART: RTS#. Bit-bang: D2. |
| 54 | DDBUS3 | bidirectional | Channel D bit 3. UART: CTS#. Bit-bang: D3. |
| 55 | DDBUS4 | bidirectional | Channel D bit 4. UART: DTR#. Bit-bang: D4. |
| 56 | VCCIO | power_in | +3.3 V I/O interface power supply input. All VCCIO pins must be connected. |
| 57 | DDBUS5 | bidirectional | Channel D bit 5. UART: DSR#. Bit-bang: D5. |
| 58 | DDBUS6 | bidirectional | Channel D bit 6. UART: DCD#. Bit-bang: D6. |
| 59 | DDBUS7 | bidirectional | Channel D bit 7. UART: RI# or TXDEN (EEPROM-selectable). Bit-bang: D7. |
| 60 | PWREN# | output | Active-low power-enable output. Low = normal operation; high = USB suspend or device not yet configured. Useful for gating external supplies. |
| 61 | EEDATA | bidirectional | External serial EEPROM data I/O. Connects to the EEPROM DI directly and to EEPROM DO through a 2.2 kΩ resistor; DO also pulled up to VCC with 10 kΩ. Tri-state during device reset. |
| 62 | EECLK | output | External serial EEPROM clock output. Tri-state during device reset. |
| 63 | EECS | bidirectional | External serial EEPROM chip-select. Tri-state during device reset. |
| 64 | VCORE | power_in | +1.8 V core supply input. Tie to VREGOUT (pin 49) with the other VCORE pins. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | FTDI |
| Package | LQFP-64(10x10) |
| Category | Interface |
| Pins | 64 |
Ordering variants
FT4232HL-ReelFT4232HL-ReelTray
CAD (KiCad official)
- Symbol:
FT4232HL-Reel - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: FTDI datasheet (None pp, sha256
19462d37a9d1e484, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).