FT232HL-REEL from FTDI, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OSCI	input	Oscillator input. Connect the 12 MHz crystal reference across OSCI/OSCO (with load caps), or drive from an external clock source.
2	OSCO	output	Oscillator output for the 12 MHz crystal. Connect to the far side of the crystal with its load capacitor to GND; leave floating when using an external clock on OSCI.
3	VPHY	power_in	+3.3V input, internal USB PHY supply. Must NOT be connected directly to the USB VBUS supply; use a 3.3V regulator and filter with an LC filter (see section 6.1).
4	AGND	power_in	0V analog ground. Tie all AGND pins to the board ground plane.
5	REF	passive	Analog current reference. Connect a 12KΩ 1% resistor from this pin to GND to set the internal bias current.
6	DM	bidirectional	USB 2.0 differential data signal minus (D-). Connect to the USB connector D- through the recommended series/EMI network.
7	DP	bidirectional	USB 2.0 differential data signal plus (D+). Connect to the USB connector D+ through the recommended series/EMI network.
8	VPLL	power_in	+3.3V input, internal PLL supply. Recommended to be filtered with an LC filter from the same 3.3V rail as VPHY (see section 6.1).
9	AGND	power_in	0V analog ground.
10	GND	power_in	0V digital ground.
11	GND	power_in	0V digital ground.
12	VCCIO	power_in	+3.3V I/O interface power supply input. Sets the output voltage level for all ADBUS and ACBUS pins.
13	ADBUS0	bidirectional	Bus A bit 0. Default UART: TXD (async serial transmit). Reconfigurable to D0 (FT245 sync/async FIFO, bit-bang, CPU FIFO), TCK/SK (MPSSE JTAG/SPI clock), FSDI (fast serial data in) or MIOSI0 (FT1248).
14	ADBUS1	bidirectional	Bus A bit 1. Default UART: RXD (async serial receive). Reconfigurable to D1 (FIFO/bit-bang), TDI/DO (MPSSE), FSCLK (fast serial clock) or MIOSI1 (FT1248).
15	ADBUS2	bidirectional	Bus A bit 2. Default UART: RTS# (request-to-send, active low). Reconfigurable to D2, TDO/DI (MPSSE), FSDO or MIOSI2 (FT1248).
16	ADBUS3	bidirectional	Bus A bit 3. Default UART: CTS# (clear-to-send input, active low). Reconfigurable to D3, TMS/CS (MPSSE), FSCTS or MIOSI3 (FT1248).
17	ADBUS4	bidirectional	Bus A bit 4. Default UART: DTR# (data-terminal-ready output, active low). Reconfigurable to D4, GPIOL0 (MPSSE), fast-serial TriSt-UP, or MIOSI4 (FT1248).
18	ADBUS5	bidirectional	Bus A bit 5. Default UART: DSR# (data-set-ready input, active low). Reconfigurable to D5, GPIOL1 (MPSSE), TriSt-UP or MIOSI5 (FT1248).
19	ADBUS6	bidirectional	Bus A bit 6. Default UART: DCD# (data-carrier-detect input, active low). Reconfigurable to D6, GPIOL2 (MPSSE), TriSt-UP or MIOSI6 (FT1248).
20	ADBUS7	bidirectional	Bus A bit 7. Default UART: RI# (ring indicator input, active low). Taking RI# low can wake the PC USB host from suspend when remote wake-up is enabled in EEPROM. Reconfigurable to D7, GPIOL3 (MPSSE) or MIOSI7 (FT1248).
21	ACBUS0	bidirectional	Configurable ACBUS I/O pin. Default TXDEN (RS485 driver enable) when EEPROM sets that option, otherwise TriState with 75KΩ pull-up to VCCIO. EEPROM-selectable to PWREN#, TXLED#, RXLED#, TX&RXLED#, SLEEP#, CLK30/15/7.5, DRIVE0/1 (see Table 3.5).
22	GND	power_in	0V digital ground.
23	GND	power_in	0V digital ground.
24	VCCIO	power_in	+3.3V I/O interface power supply input. Sets output level for the ADBUS/ACBUS pins on this side of the die.
25	ACBUS1	bidirectional	Configurable ACBUS I/O pin. Default tri-state input with 75KΩ pull-up to VCCIO; commonly used for TXE#, WRSTB#, GPIOH1, A0 (CPU FIFO) or SS_n (FT1248). EEPROM-selectable to any ACBUS signal in Table 3.5.
26	ACBUS2	bidirectional	Configurable ACBUS I/O pin. Default tri-state input with 75KΩ pull-up to VCCIO; RD#, RDSTB#, GPIOH2 or MISO (FT1248) in the various modes. EEPROM-selectable to any ACBUS signal in Table 3.5.
27	ACBUS3	bidirectional	Configurable ACBUS I/O pin. Default RXLED# when EEPROM selects it, else tri-state pull-up. In other modes: WR#, GPIOH3 or ACBUS3 (FT1248).
28	ACBUS4	bidirectional	Configurable ACBUS I/O pin. Default TXLED# when EEPROM selects it, else SIWU# (Send-Immediate/Wake-Up input) in most FIFO/serial modes, or GPIOH4 in MPSSE.
29	ACBUS5	bidirectional	Configurable ACBUS I/O pin. In Sync FIFO mode: CLKOUT (60 MHz FIFO clock output). Otherwise tri-state pull-up input or GPIOH5 (MPSSE).
30	ACBUS6	bidirectional	Configurable ACBUS I/O pin. In Sync FIFO mode: OE# (output enable, active low). Otherwise tri-state pull-up input or GPIOH6 (MPSSE).
31	ACBUS7	bidirectional	Configurable ACBUS I/O pin. Default PWRSAV# / PWRSAV# in most modes, or WRSAV# (UART) / GPIOH7 (MPSSE). Defaults to GPIO line with an internal 75KΩ pull-down to GND (can be switched to USBVCC mode via EEPROM).
32	ACBUS8	bidirectional	Configurable ACBUS I/O pin. Default tri-state input with 75KΩ pull-up to VCCIO; EEPROM-selectable to any ACBUS signal in Table 3.5 (bit-bang capable).
33	ACBUS9	bidirectional	Configurable ACBUS I/O pin. Default tri-state input with 75KΩ pull-up to VCCIO; EEPROM-selectable to any ACBUS signal in Table 3.5 (bit-bang capable).
34	RESET#	input	Chip reset input, active low. Tie to VCCIO through a pull-up (typically 10KΩ) or leave high for normal operation.
35	GND	power_in	0V digital ground.
36	GND	power_in	0V digital ground.
37	VCCA	power_out	+1.8V LDO output for the analog core. Do not use as a supply for external circuitry; terminate with a 0.1uF ceramic capacitor to GND.
38	VCCCORE	power_out	+1.8V LDO output for the digital core. Do not use as a supply for external circuitry; terminate with a 0.1uF ceramic capacitor to GND.
39	VCCD	bidirectional	+3.3V output OR input. If VREGIN (pin 40) is driven at +5.0V, VCCD becomes an LDO OUTPUT (~3.3V, decouple with 0.1uF/4.7uF). If VREGIN is driven at +3.3V, VCCD becomes an INPUT that must be tied to the 3.3V rail.
40	VREGIN	power_in	+5.0V or +3.3V power supply input to the internal LDO. Feed from the USB VBUS (via a bulk cap) in bus-powered designs, or from a regulated 3.3V rail in self-powered designs.
41	AGND	power_in	0V analog ground.
42	TEST	input	IC test pin. Must be tied to GND for normal operation; leaving it floating puts the FT232H into a factory test mode.
43	EEDATA	bidirectional	Serial data to/from the external 93C46/93C56/93C66 EEPROM. Connect directly to the EEPROM DI pin AND to DO through a 2.2KΩ series resistor; also pull DO up to VCCD with 10KΩ. Tri-stated during device reset.
44	EECLK	output	Clock output to the external EEPROM (SK pin). Tri-stated during device reset; drives the EEPROM SPI clock otherwise.
45	EECS	bidirectional	EEPROM chip-select output (SPI CS). Tri-stated during device reset. If no EEPROM is fitted the FT232H uses its default USB descriptors.
46	VCCIO	power_in	+3.3V I/O interface power supply input. Decouple with 0.1uF to GND.
47	GND	power_in	0V digital ground.
48	GND	power_in	0V digital ground.

Key specifications

Parameter	Value
Manufacturer	FTDI
Package	LQFP-48(7x7)
Category	Interface
Pins	48

Ordering variants

Same part, different packaging or reel option.

FT232HL-Reel
FT232HL-Tray
FT232HQ-Reel
FT232HQ-Tray

CAD (KiCad official)

Symbol: FT232HL-REEL
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: FTDI datasheet (65 pp, sha256 7976683a05f00181, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF