FSV9563 from Forsinve, in a QFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	TDO	output	Test data output for boundary scan (JTAG) interface.
2	TDI	input	Test data input for boundary scan (JTAG) interface.
3	TMS	input	Test mode select for boundary scan (JTAG) interface.
4	TCK	input	Test clock for boundary scan (JTAG) interface.
5	SIGIN	input	Contactless communication interface input signal.
6	SIGOUT	output	Contactless communication interface output signal.
7	DVDD	power_in	Digital power supply buffer. Requires an external buffer capacitor; do not connect a supply voltage.
8	VDD	power_in	Main power supply, 3.0 V to 5.5 V (typ 5 V).
9	AVDD	power_in	Analog power supply buffer. Requires an external buffer capacitor; do not connect a supply voltage.
10	AUX1	output	Auxiliary output; used for analog test signal.
11	AUX2	output	Auxiliary output; used for analog test signal.
12	RXP	input	Receiver input (positive) for the received RF signal from the antenna.
13	RXN	input	Receiver input (negative) for the received RF signal from the antenna.
14	VMID	power_out	Internal receiver reference voltage. Requires an external buffer capacitor; do not connect a supply voltage.
15	TX2	output	Transmitter output 2; delivers the modulated 13.56 MHz carrier to the antenna matching network.
16	TVSS	power_in	Transmitter ground; supplies the output stage of TX1 and TX2.
17	TX1	output	Transmitter output 1; delivers the modulated 13.56 MHz carrier to the antenna matching network.
18	TVDD	power_in	Transmitter voltage supply for the TX1/TX2 output stage; 3.0 V to 5.5 V (typ 5 V).
19	XTAL1	input	Crystal oscillator input to the inverting amplifier. Also the input for an externally generated clock (fosc = 27.12 MHz).
20	XTAL2	output	Crystal oscillator output from the inverting amplifier (27.12 MHz).
21	PDOWN	input	Power Down input. Drive HIGH to place the device into hard power-down (Ipd ~8 nA).
22	CLKOUT	output	Clock output derived from the internal PLL/oscillator, available to drive an external host or peripheral.
23	SCL	output	Dedicated I2C serial clock line for the connection of a Secure Access Module (SAM).
24	SDA	bidirectional	Dedicated I2C serial data line for the connection of a Secure Access Module (SAM).
25	PVDD	power_in	Pad power supply; sets the I/O voltage level. Must be equal to or lower than VDD (3.0 V to VDD).
26	IFSEL0	input	Host interface selection 0. Combined with IFSEL1 selects the host interface protocol assigned to IF0-IF3 (RS232 UART, SPI, I2C, or I2C-L).
27	IFSEL1	input	Host interface selection 1. Combined with IFSEL0 selects the host interface protocol assigned to IF0-IF3 (RS232 UART, SPI, I2C, or I2C-L).
28	IF0	bidirectional	Multifunction host interface pin. Function assigned by IFSEL0/IFSEL1: RS232 UART, SPI, I2C or I2C-L.
29	IF1	bidirectional	Multifunction host interface pin. Function assigned by IFSEL0/IFSEL1: SPI, I2C or I2C-L.
30	IF2	bidirectional	Multifunction host interface pin. Function assigned by IFSEL0/IFSEL1: RS232 UART, SPI, I2C or I2C-L.
31	IF3	bidirectional	Multifunction host interface pin. Function assigned by IFSEL0/IFSEL1: RS232 UART, SPI, I2C or I2C-L.
32	IRQ	output	Interrupt request output; asserted to signal an interrupt event to the host.
33	VSS	power_in	Ground and central heatsink (exposed pad) connection. Must be soldered to the PCB ground for thermal and electrical grounding.

Key specifications

Parameter	Value
Manufacturer	Forsinve
Package	QFN-32(5x5)
Category	RF And Wireless
Pins	33

CAD (KiCad official)

Symbol: FSV9563
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: QFN-32(5x5) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Forsinve datasheet (126 pp, sha256 afcac6211805fff2, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF