ES7241D from Everest semi Everest Semiconductor, in a QFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDDP	power_in	Power supply for the digital input and output. Recommended 1.6 V to 3.6 V (typ 3.3 V). Decoupling capacitors (100 nF) should be placed close to the pin.
2	SDOUT	output	Serial data output from the ADC. Audio data output on the falling edge of SCLK. Format selection: pull-up resistor at SDOUT selects I2S; pull-down resistor selects left-justified format.
3	GNDD	power_in	Digital ground reference. Connect to system ground plane; in layout the chip should be treated as an analog device with AGND connected to system GND via 0Ω.
4	VDDD	power_in	Digital power supply. Recommended 3.0 V to 3.6 V (typ 3.3 V). Requires 100 nF decoupling capacitor close to the pin.
5	SCLK	bidirectional	Serial data bit clock. Direction depends on M1:M0 mode selection - output in master mode (derived internally from MCLK) or input in slave mode. SCLK/LRCK ratio is normally 64; maximum frequency 26 MHz.
6	LRCK	bidirectional	Serial data left/right channel frame clock (word clock). Output in master mode, input in slave mode. Maximum frequency 200 kHz; duty cycle 40-60%.
7	RESETb	input	Active-low chip reset. Drive low to place device in low-power reset/power-down. Must be held low during power-up until supplies, clocks and mode-select pins are stable.
8	AINL	input	Analog left channel input to the delta-sigma modulator. Full-scale input level 1.084 Vrms (3 Vpp); input impedance 20 kΩ. AC-couple with 1 µF capacitor.
9	REFQ	passive	Reference filtering capacitor connection. Connect a 1 µF filtering capacitor to AGND close to the pin for best performance.
10	AINR	input	Analog right channel input to the delta-sigma modulator. Full-scale input level 1.084 Vrms (3 Vpp); input impedance 20 kΩ. AC-couple with 1 µF capacitor.
11	VDDA	power_in	Analog power supply for the ADC and reference circuits. Recommended 3.0 V to 3.6 V (typ 3.3 V). Requires 1 µF (and optionally 100 nF parallel) decoupling to AGND close to the pin.
12	GNDA	power_in	Analog ground reference for the ADC. Connect to system ground plane via a 0 Ω link; chip is treated as an analog device in layout.
13	REFP	passive	Reference filtering capacitor connection. Connect a 1 µF filtering capacitor (optionally paralleled with 100 nF) to AGND close to the pin.
14	M1	input	Mode selection bit 1. With M0 forms a 2-bit code: 00=master single speed, 01=master double speed, 10=master quad speed, 11=slave mode (all speeds). Sample the pin state at reset.
15	M0	input	Mode selection bit 0. Together with M1 selects master/slave clock mode and single/double/quad speed operation (see Table 1).
16	MCLK	input	Master clock input to the clock manager / sample-rate detector. Maximum 51.2 MHz, duty cycle 40-60%. In master mode LRCK and SCLK are derived internally from MCLK.
17	PGND	power_in	Exposed thermal/ground pad on QFN bottom (center paddle). Connect to AGND for proper thermal dissipation and grounding.

Key specifications

Parameter	Value
Manufacturer	Everest semi Everest Semiconductor
Package	QFN-16-EP(3x3)
Category	Interface
Pins	17

Ordering variants

Same part, different packaging or reel option.

ES7241D

CAD (KiCad official)

Symbol: ES7241D
Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
3D model: QFN-16-EP(3x3) (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`es7241d.step`	190 KB	You want the bare part, or you mark your own boards.
`es7241d-etched.step`	1.3 MB	You want the part with `ES7241D` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 347 faces against 110 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Everest semi Everest Semiconductor datasheet (10 pp, sha256 9ea48093a9982ecc, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF