EG1151 from EG Micro, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD12	power_in	Gate-driver module power supply input (nominally 12 V rail feeding the half-bridge drivers).
2	IFB+	input	Positive input of the output-current sense op-amp; connect across the current-sense resistor.
3	IFB-	input	Negative input of the output-current sense op-amp; connect across the current-sense resistor.
4	NC	unconnected	No connect. Leave floating.
5	NC	unconnected	No connect. Leave floating.
6	SWCLK	input	Firmware upgrade clock (SWD-style programming interface).
7	SWDIO	input	Firmware upgrade data (SWD-style programming interface).
8	VINFB	input	Input-voltage sense/feedback. Connect via divider to VIN for input-voltage monitoring and UVLO.
9	RSTN	input	Chip reset input, active low.
10	AVSS	power_in	Analog/chip ground.
11	AVDD	power_in	Analog/chip power supply input.
12	LDO15	power_out	Internal 1.5 V LDO output; requires an external 0.1 µF decoupling capacitor to GND.
13	VOUTFB	input	Output-voltage feedback input; connect via resistor divider from VOUT to set the regulation setpoint.
14	TFB	input	Temperature-sense feedback input (typically for an external NTC).
15	NC	unconnected	No connect. Leave floating.
16	NC	unconnected	No connect. Leave floating.
17	NC	unconnected	No connect. Leave floating.
18	NC	unconnected	No connect. Leave floating.
19	NC	unconnected	No connect. Leave floating.
20	PGND	power_in	Power ground for the gate-driver module.
21	Reserved	unconnected	Reserved pin per datasheet. Leave unconnected unless otherwise noted.
22	LO2	output	Right-bridge low-side gate driver output (drives low-side MOSFET of the right half-bridge).
23	LO1	output	Left-bridge low-side gate driver output (drives low-side MOSFET of the left half-bridge).
24	Reserved	unconnected	Reserved pin per datasheet. Leave unconnected unless otherwise noted.
25	Reserved	unconnected	Reserved pin per datasheet. Leave unconnected unless otherwise noted.
26	Reserved	unconnected	Reserved pin per datasheet. Leave unconnected unless otherwise noted.
27	VS2	output	Right-bridge high-side floating source/switch node (bootstrap reference for HO2).
28	HO2	output	Right-bridge high-side gate driver output (drives high-side MOSFET of the right half-bridge).
29	VB2	power_in	Right-bridge high-side bootstrap supply; connect an external bootstrap capacitor between VB2 and VS2.
30	VS1	output	Left-bridge high-side floating source/switch node (bootstrap reference for HO1).
31	HO1	output	Left-bridge high-side gate driver output (drives high-side MOSFET of the left half-bridge).
32	VB1	power_in	Left-bridge high-side bootstrap supply; connect an external bootstrap capacitor between VB1 and VS1.

Key specifications

Parameter	Value
Manufacturer	EG Micro
Package	QFN-32-EP(5x5)
Category	PMIC
Pins	32

CAD (KiCad official)

Symbol: EG1151
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: EG Micro datasheet (12 pp, sha256 4f75e18e89102be4, retrieved 2026-08-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF