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DS90UB953ATRHBTQ1

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Texas Instruments Serializers, Deserializers, VQFN-32(5x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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DS90UB953ATRHBTQ1

Texas Instruments · Serializers, Deserializers · VQFN-32(5x5)

DS90UB953ATRHBTQ1 from Texas Instruments, in a VQFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CSI_D1P input CSI-2 D-PHY data lane 1 positive input. Connect to a CSI-2 data source through a 100Ω (±5%) matched-impedance interconnect. May be left floating if unused.
2 CSI_D1N input CSI-2 D-PHY data lane 1 negative input. Pair with CSI_D1P over 100Ω matched-impedance. May be left floating if unused.
3 CSI_D0P input CSI-2 D-PHY data lane 0 positive input. Connect to a CSI-2 data source through a 100Ω (±5%) matched-impedance interconnect.
4 CSI_D0N input CSI-2 D-PHY data lane 0 negative input. Pair with CSI_D0P.
5 CSI_CLKP input CSI-2 D-PHY clock positive input. Connect to a CSI-2 clock source with 100Ω (±5%) matched-impedance interconnect.
6 CSI_CLKN input CSI-2 D-PHY clock negative input. Pair with CSI_CLKP.
7 RES0 input Reserved pin - must be tied to GND.
8 PDB input Active-low power-down / device enable input, internally pulled down (~1MΩ). Drive high to enable the device (typically tied to a processor GPIO). Do NOT drive above VDD (1.8V); PDB is NOT 3.3V tolerant. PDB=1.8V: device operating; PDB=0: device disabled.
9 LPF1 passive PLL loop filter 1 network connection. Populate per section 7.2.2.4.
10 VDDPLL_CAP passive Internal analog LDO decoupling capacitor connection. Typically bypass with 10µF, 0.1µF and 0.01µF caps to GND. Do NOT connect to an external supply rail.
11 VDDPLL power_in 1.8V (±5%) analog PLL supply. Bypass with 1µF cap to GND.
12 LPF2 passive PLL loop filter 2 network connection. Populate per section 7.2.2.4.
13 DOUT- bidirectional FPD-Link III serial link negative I/O. AC-couple this pin as shown in Figure 7-3/7-5/7-6.
14 DOUT+ bidirectional FPD-Link III serial link positive I/O. AC-couple this pin as shown in the reference circuits.
15 VDDDRV_CAP passive Internal analog LDO decoupling capacitor connection for the driver rail. Typically bypass with 10µF, 0.1µF and 0.01µF caps to GND. Do NOT connect to an external supply.
16 VDDDRV power_in 1.8V (±5%) analog driver supply. Bypass with 1µF cap to GND.
17 GPIO_0 bidirectional General-purpose I/O; also usable as a voltage-sense input. Internal ~300kΩ pull-down default. If unused, may be left open, but TI recommends setting GPIOx_INPUT_EN=0.
18 GPIO_1 bidirectional General-purpose I/O; also usable as a voltage-sense input. Internal ~300kΩ pull-down default.
19 CLK_OUT/IDX bidirectional Strap-configured I/O: at power-up an IDX voltage divider (external pull-up to VDD and pull-down to GND) sets the I2C address; after strap sampling the pin becomes CLK_OUT. Minimum external pull-up 35kΩ; tie to GND if unused.
20 CLKIN input Reference clock input. In non-synchronous external clock mode connect this pin to a local clock source; otherwise (synchronous with FPD-Link clock) leave open. See section 6-8.
21 MODE input Mode-select strap input sampled during PDB low-to-high transition to select operating configuration. Set via an external pull-up to VDD18 and pull-down to GND to create a voltage divider. See MODE section for details.
22 RES1 input Reserved pin - leave unconnected (open).
23 I2C_SDA bidirectional I2C data pin, open-drain. Pull up to a 1.8V or 3.3V supply per the IDX setting. See I2C interface configuration and SVLA689 for pull-up sizing.
24 I2C_SCL bidirectional I2C clock pin, open-drain. Pull up per the IDX setting (1.8V or 3.3V).
25 VDDD power_in 1.8V (±5%) digital supply. Bypass with 1µF cap to GND.
26 VDDD_CAP passive Internal digital LDO decoupling capacitor pin. Typically bypass with 10µF, 0.1µF and 0.01µF caps to GND. Do NOT connect to an external supply.
27 GPIO_2 bidirectional General-purpose I/O with internal ~300kΩ pull-down at reset. May be left open if unused; TI recommends GPIOx_INPUT_EN=0 in that case.
28 GPIO_3 bidirectional General-purpose I/O with internal ~300kΩ pull-down at reset.
29 CSI_D3P input CSI-2 D-PHY data lane 3 positive input. Connect to a CSI-2 data source through a 100Ω (±5%) matched-impedance interconnect. May be left floating if unused.
30 CSI_D3N input CSI-2 D-PHY data lane 3 negative input.
31 CSI_D2P input CSI-2 D-PHY data lane 2 positive input. Connect to a CSI-2 data source through a 100Ω (±5%) matched-impedance interconnect.
32 CSI_D2N input CSI-2 D-PHY data lane 2 negative input.
DAP GND power_in Die attach pad - large metal contact on the bottom center of the VQFN. Must be connected to the ground plane (GND) for electrical return and thermal dissipation.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32(5x5)
Category Interface
Pins 33

Ordering variants

Same part, different packaging or reel option.

  • DS90UB953ATRHBTQ1
  • DS90UB953ATRHBTQ1RHBRQ1

CAD (KiCad official)

  • Symbol: DS90UB953ATRHBTQ1
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32(5x5) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (94 pp, sha256 370a551290974f6a, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF