DS1302CDRG from HANSCHIP semiconductor, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VCC2	power_in	Primary (main) power supply input, 2.0 V to 5.5 V. When VCC2 > VCC1 + 0.2 V, the device is powered from VCC2 and can source the trickle charger to VCC1.
2	X1	passive	Connection for a 32.768 kHz quartz crystal. Internal oscillator load capacitance is ~6 pF; external crystal typically 6 pF CL.
3	X2	passive	Connection for the other terminal of the 32.768 kHz quartz crystal. Pairs with X1 to form the timekeeping oscillator.
4	GND	power_in	Device ground reference (0 V).
5	RST	input	Active-high reset / chip-enable input. Must be driven high to initiate any data transfer; while low all transfers are terminated and I/O goes high-impedance. TTL compatible at VCC=5 V.
6	I/O	bidirectional	Bidirectional serial data pin for the 3-wire interface. Command/data bytes are clocked in on SCLK rising edges (LSB first) and read data is driven on SCLK falling edges. Tri-stated when RST is low or between bit phases.
7	SCLK	input	Serial clock input for the 3-wire bus. Max 2.0 MHz at VCC=5 V, 0.5 MHz at VCC=2.5 V. Must be low when RST is driven high.
8	VCC1	power_in	Backup power supply input (typically a battery or super-cap). Powers the RTC when VCC2 falls below VCC1; also the sink node of the optional on-chip trickle charger from VCC2.

Key specifications

Parameter	Value
Manufacturer	HANSCHIP semiconductor
Package	SOP-8
Category	RTC
Pins	8

Ordering variants

Same part, different packaging or reel option.

DS1302CDRG
DS1302CDRGIDRG
DS1302CDRG4
DS1302CDRGIDRG4
DS1302CDRGCPG
DS1302CDRGIPG
DS1302CDRGCDGKRG
DS1302CDRGIDGKRG

CAD (KiCad official)

Symbol: DS1302CDRG
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOP-8 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`ds1302cdrg.step`	122 KB	You want the bare part, or you mark your own boards.
`ds1302cdrg-etched.step`	2.4 MB	You want the part with `DS1302CDRG` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 576 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: HANSCHIP semiconductor datasheet (15 pp, sha256 6dfca75d1e1627dd, retrieved 2026-08-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF