DRV8908QPWPRQ1 from Texas Instruments, in a HTSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GND	power_in	Device power ground. Connect to system ground.
2	OUT1	output	Half-bridge 1 output. Drives up to 1 A RMS (6 A when paralleled), 4.5-32 V (40 V abs max).
3	OUT5	output	Half-bridge 5 output. Drives up to 1 A RMS (6 A when paralleled).
4	OUT7	output	Half-bridge 7 output. Drives up to 1 A RMS (6 A when paralleled).
5	SDI	input	SPI serial data input (MOSI). Captured on the falling edge of SCLK. Internal pull-down.
6	VDD	power_in	Logic power supply input (3.3 V or 5 V). Bypass with a 0.1-µF X5R/X7R ceramic close to the pin and ≥ 1-µF bulk capacitance to GND.
7	SDO	output	SPI serial data output (MISO), push-pull. Data is shifted out on the rising edge of SCLK.
8	nSLEEP	input	Active-low driver enable. Logic low places the device in low-power sleep mode. Internal pull-down.
9	NC	unconnected	Not connected on the DRV8908-Q1 variant. Leave floating or tie to GND.
10	OUT6	output	Half-bridge 6 output. Drives up to 1 A RMS (6 A when paralleled).
11	OUT4	output	Half-bridge 4 output. Drives up to 1 A RMS (6 A when paralleled).
12	nFAULT	output	Active-low fault indicator, open-drain. Pulled low on any fault condition; requires an external pull-up resistor to VDD.
13	GND	power_in	Device power ground. Connect to system ground.
14	OUT3	output	Half-bridge 3 output. Drives up to 1 A RMS (6 A when paralleled).
15	NC	unconnected	Not connected on the DRV8908-Q1 variant.
16	VM	power_in	Main motor supply input (4.5-32 V, 40 V abs max). Tie both VM pins together and bypass with 0.1-µF X5R/X7R ceramic plus ≥ 10-µF bulk to GND.
17	NC	unconnected	Not connected on the DRV8908-Q1 variant.
18	NC	unconnected	Not connected on the DRV8908-Q1 variant.
19	nSCS	input	SPI chip-select (active-low). Logic low enables serial interface communication. Internal pull-up.
20	SCLK	input	SPI serial clock input, up to 5 MHz. Data shifted on rising edge, captured on falling edge. Internal pull-down.
21	VM	power_in	Main motor supply input (4.5-32 V). Tie both VM pins together and bypass with 0.1-µF X5R/X7R ceramic plus ≥ 10-µF bulk to GND.
22	OUT8	output	Half-bridge 8 output. Drives up to 1 A RMS (6 A when paralleled).
23	OUT2	output	Half-bridge 2 output. Drives up to 1 A RMS (6 A when paralleled).
24	GND	power_in	Device power ground. Connect to system ground. Exposed thermal pad on the package underside must also be tied to GND for heat dissipation.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	HTSSOP-24
Category	PMIC
Pins	24

Ordering variants

Same part, different packaging or reel option.

DRV8908QPWPRQ1
DRV8912-Q1
DRV8910-Q1
DRV8906-Q1
DRV8904-Q1

CAD (KiCad official)

Symbol: DRV8908QPWPRQ1
Footprint: Package_SO:HTSSOP-24-1EP_4.4x7.8mm_P0.65mm_EP3.4x7.8mm_Mask2.4x4.68mm
3D model: HTSSOP-24 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (157 pp, sha256 a77f05c6f973795d, retrieved 2026-08-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF