DP83867CRRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	TD_P_A	bidirectional	Media Dependent Interface: Differential transmit/receive pair A (positive). Connects through magnetics to RJ45.
2	TD_M_A	bidirectional	Media Dependent Interface: Differential transmit/receive pair A (negative).
3	VDDA2P5	power_in	2.5V analog supply (±5%). Requires 1µF + 0.1µF decoupling to GND.
4	TD_P_B	bidirectional	Media Dependent Interface: Differential transmit/receive pair B (positive).
5	TD_M_B	bidirectional	Media Dependent Interface: Differential transmit/receive pair B (negative).
6	VDD1P0	power_in	1.0V digital core supply (+15.5%, -5%). Requires 1µF + 0.1µF decoupling to GND.
7	TD_P_C	bidirectional	Media Dependent Interface: Differential transmit/receive pair C (positive).
8	TD_M_C	bidirectional	Media Dependent Interface: Differential transmit/receive pair C (negative).
9	VDDA2P5	power_in	2.5V analog supply (±5%). Requires 1µF + 0.1µF decoupling to GND.
10	TD_P_D	bidirectional	Media Dependent Interface: Differential transmit/receive pair D (positive).
11	TD_M_D	bidirectional	Media Dependent Interface: Differential transmit/receive pair D (negative).
12	RBIAS	passive	Bias resistor connection. Connect an 11kΩ ±1% resistor from RBIAS to GND to set internal reference currents.
13	VDDA1P8	power_in	1.8V analog supply (±5%). May be left unconnected (internal LDO) or driven with external 1.8V for lower power; when driven, requires 1µF + 0.1µF to GND.
14	XO	output	Crystal output. Second terminal for the 25MHz crystal. Leave floating when driving XI from an external oscillator.
15	XI	input	Crystal/oscillator input. 25MHz reference (±50 ppm), from crystal (with XO) or single-ended oscillator.
16	MDC	input	MII Management Data Clock. Synchronous clock for MDIO transfers, up to 25MHz. Internal pull-down.
17	MDIO	bidirectional	MII Management Data I/O. Bi-directional management data line. External pull-up required (1.5kΩ per IEEE, 2.2kΩ acceptable) to VDDIO.
18	CLK_OUT	output	Programmable clock output (default 25MHz or 125MHz synchronous Ethernet reference).
19	VDDIO	power_in	Digital I/O supply. Selectable 1.8V, 2.5V, or 3.3V (±5%). Requires 1µF + 0.1µF to GND.
20	JTAG_CLK	input	JTAG TCK. IEEE 1149.1 test clock input. Internal pull-up.
21	JTAG_TDO	output	JTAG TDO. IEEE 1149.1 test data output.
22	JTAG_TMS	input	JTAG TMS. IEEE 1149.1 test mode select. Internal pull-up.
23	JTAG_TDI	input	JTAG TDI. IEEE 1149.1 test data input. Internal pull-up.
24	VDD1P0	power_in	1.0V digital core supply (+15.5%, -5%).
25	TX_D3	input	RGMII/GMII/MII transmit data bit 3, sourced by MAC. Synchronous to GTX_CLK (RGMII/GMII) or TX_CLK (MII). Internal pull-down.
26	TX_D2	input	RGMII/GMII/MII transmit data bit 2. Synchronous to GTX_CLK (RGMII/GMII) or TX_CLK (MII). Internal pull-down.
27	TX_D1	input	RGMII/GMII/MII transmit data bit 1. Internal pull-down.
28	TX_D0	input	RGMII/GMII/MII transmit data bit 0. Internal pull-down.
29	GTX_CLK	input	GMII/RGMII transmit clock, 125MHz nominal, sourced from MAC to PHY. Internal pull-down.
30	VDDIO	power_in	Digital I/O supply. Selectable 1.8V, 2.5V, or 3.3V (±5%).
31	VDD1P0	power_in	1.0V digital core supply (+15.5%, -5%).
32	RX_CLK	output	Receive clock recovered from the line: 2.5MHz (10Mbps), 25MHz (100Mbps), 125MHz (1000Mbps/RGMII).
33	RX_D0	output	Receive data bit 0, PHY to MAC. Synchronous to RX_CLK. Also a strap-configuration pin at reset.
34	RX_D1	output	Receive data bit 1, PHY to MAC. Synchronous to RX_CLK.
35	RX_D2	output	Receive data bit 2, PHY to MAC. Also a strap-configuration pin at reset.
36	RX_D3	output	Receive data bit 3, PHY to MAC. Synchronous to RX_CLK.
37	TX_EN/TX_CTRL	input	MII/GMII transmit enable, or RGMII TX_CTRL (combined enable + error on dual clock edges). Internal pull-down.
38	RX_DV/RX_CTRL	output	MII/GMII receive data valid, or RGMII RX_CTRL (combined DV + ER on dual clock edges). Also a strap pin.
39	GPIO_0	bidirectional	General-purpose configurable I/O; function selected via GPIO_MUX_CTRL register. Also a strap pin at reset.
40	GPIO_1	bidirectional	General-purpose configurable I/O; function selected via GPIO_MUX_CTRL register. Also a strap pin at reset.
41	VDDIO	power_in	Digital I/O supply. Selectable 1.8V, 2.5V, or 3.3V (±5%).
42	VDD1P0	power_in	1.0V digital core supply (+15.5%, -5%).
43	RESET_N	input	Active-low hardware reset. Assert low for ≥1µs to reset all internal registers to defaults. Internal pull-up.
44	INT/PWDN	bidirectional	Dual-function interrupt output / power-down input. Default is active-low power-down; can be reconfigured via register as active-low open-drain interrupt (needs 2.2kΩ pull-up to VDDIO). Internal pull-up.
45	LED_2	bidirectional	LED_2 status output; default and alternate functions configurable via LEDCR1[11:8]. Also a strap pin.
46	LED_1	bidirectional	LED_1 status output; defaults to 1000BASE-T link indication. Alternate function via LEDCR1[7:4]. Also a strap pin.
47	LED_0	bidirectional	LED_0 status output; defaults to link-established indication. Alternate function via LEDCR1[3:0]. Also a strap pin.
48	VDDA1P8	power_in	1.8V analog supply (±5%). May be left unconnected (internal LDO) or driven externally with 1µF + 0.1µF decoupling.
49	GND	power_in	Exposed die-attach thermal pad. Must be soldered to the PCB ground plane for thermal and electrical performance.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-48-EP(7x7)
Category	Interface
Pins	49

Ordering variants

Same part, different packaging or reel option.

DP83867CRRGZR
DP83867CRRGZT
DP83867CRRGZRIRRGZ
DP83867CRRGZRIRRGZR
DP83867CRRGZRIRRGZT
DP83867CRRGZRIRPAP
DP83867CRRGZRIRPAPR
DP83867CRRGZRIRPAPT

CAD (KiCad official)

Symbol: DP83867CRRGZR
Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`dp83867crrgzr.step`	526 KB	You want the bare part, or you mark your own boards.
`dp83867crrgzr-etched.step`	3.7 MB	You want the part with `DP83867CRRGZR` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 899 faces against 302 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (143 pp, sha256 f800269111b22ad7, retrieved 2026-08-17, tier: manufacturer)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF