DP83848IVVX from Texas Instruments, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	TX_CLK	output	MII transmit clock output: 25 MHz in 100 Mb/s mode, 2.5 MHz in 10 Mb/s mode. In SNI mode provides 10 MHz. Unused in RMII (device uses X1 as 50 MHz reference).
2	TX_EN	input	MII/RMII/SNI transmit enable, active high; indicates valid data on TXD lines. Internal pulldown.
3	TXD_0	input	MII/RMII/SNI transmit data bit 0, synchronous to TX_CLK (MII/SNI) or 50 MHz reference (RMII).
4	TXD_1	input	MII/RMII transmit data bit 1, synchronous to TX_CLK (MII) or 50 MHz reference (RMII).
5	TXD_2	input	MII transmit data bit 2, synchronous to TX_CLK.
6	TXD_3/SNI_MODE	input	MII transmit data bit 3 after reset; sampled at reset as SNI_MODE strap (with MII_MODE strap it selects MII/RMII/SNI MAC interface mode). Internal pulldown.
7	PWR_DOWN/INT	bidirectional	Default POWER DOWN: active-low input to enter power-down. INTERRUPT: reconfigurable as open-drain, active-low interrupt output (requires register setup). Internal pullup.
8	TCK	input	JTAG test clock. Internal pullup. DP83848C does not support JTAG; leave unconnected on that variant.
9	TDO	output	JTAG test data output.
10	TMS	input	JTAG test mode select. Internal pullup.
11	TRST#	input	JTAG test reset, active-low asynchronous. Internal pullup.
12	TDI	input	JTAG test data input. Internal pullup.
13	RD-	bidirectional	PMD differential receive input (negative). Auto-MDIX capable - may be reconfigured as transmit output. Requires 3.3 V bias.
14	RD+	bidirectional	PMD differential receive input (positive). Auto-MDIX capable - may be reconfigured as transmit output. Requires 3.3 V bias.
15	AGND	power_in	Analog ground.
16	TD-	bidirectional	PMD differential transmit output (negative), auto-configured for 10BASE-T or 100BASE-TX. Auto-MDIX capable - may be reconfigured as receive input. Requires 3.3 V bias.
17	TD+	bidirectional	PMD differential transmit output (positive), auto-configured for 10BASE-T or 100BASE-TX. Auto-MDIX capable - may be reconfigured as receive input. Requires 3.3 V bias.
18	PFBIN1	power_in	Power feedback input 1: fed from PFBOUT via external routing; bypass with 0.1 µF close to pin. Do not connect to any other supply.
19	AGND	power_in	Analog ground.
20	RESERVED	passive	Reserved pin; must be pulled up to AVDD33 through a 2.2 kΩ resistor.
21	RESERVED	passive	Reserved pin; must be pulled up to AVDD33 through a 2.2 kΩ resistor.
22	AVDD33	power_in	Analog 3.3 V supply (3.3 V ± 0.3 V).
23	PFBOUT	power_out	Power feedback output; place 10 µF (tantalum preferred) in parallel with 0.1 µF close to this pin, then route to PFBIN1 (pin 18) and PFBIN2 (pin 37).
24	RBIAS	passive	Bias resistor connection: connect a 4.87 kΩ 1% resistor from RBIAS to GND.
25	CLK_OUT	output	Reference clock output: 25 MHz in MII mode, 50 MHz in RMII mode, so other devices can share the PHY reference clock.
26	LED_ACT/COL/AN_EN	bidirectional	After reset: Activity or Collision/Duplex LED (mode-dependent). Sampled at reset as AN_EN strap - high enables Auto-Negotiation, low forces mode selected by AN0/AN1. Internal pullup.
27	LED_SPEED/AN1	bidirectional	After reset: SPEED LED (ON at 100 Mb/s, OFF at 10 Mb/s). Sampled at reset with AN0 as advertised/forced-mode strap. Internal pullup.
28	LED_LINK/AN0	bidirectional	After reset: LINK LED (ON when link good) or LINK/ACT LED depending on mode. Sampled at reset with AN1 as advertised/forced-mode strap. Internal pullup.
29	RESET_N	input	Active-low reset: assert low for at least 1 µs to reinitialize the device. All registers return to defaults and strap options are re-latched. Internal pullup.
30	MDIO	bidirectional	MII management data I/O, bidirectional. Requires an external 1.5 kΩ pullup resistor.
31	MDC	input	MII management data clock, up to 25 MHz, no minimum rate. Asynchronous to TX/RX clocks.
32	IOVDD33	power_in	I/O 3.3 V supply.
33	X2	output	Crystal output for the reference oscillator; connect to external 25 MHz crystal across X1/X2. Leave unconnected when using an external CMOS oscillator on X1.
34	X1	input	Primary clock reference input: 25 MHz ±50 ppm crystal or CMOS oscillator (MII/SNI); 50 MHz ±50 ppm CMOS oscillator in RMII mode.
35	IOGND	power_in	I/O ground.
36	DGND	power_in	Digital ground.
37	PFBIN2	power_in	Power feedback input 2: fed from PFBOUT; bypass with 0.1 µF close to pin. Do not connect to any other supply.
38	RX_CLK	output	MII receive clock: 25 MHz recovered receive clock in 100 Mb/s mode, 2.5 MHz in 10 Mb/s mode. Provides 10 MHz in SNI mode. Unused in RMII.
39	RX_DV/MII_MODE	bidirectional	MII receive data valid (default) or RMII synchronous receive data valid. Sampled at reset as MII_MODE strap: 0=MII, 1=RMII/SNI (with SNI_MODE). Internal pulldown.
40	CRS/CRS_DV/LED_CFG	bidirectional	MII carrier sense / RMII CRS_DV / SNI carrier sense. Sampled at reset as LED_CFG strap selecting LED Mode 1 (default) or Mode 2. Internal pullup.
41	RX_ER/MDIX_EN	bidirectional	MII/RMII receive error output (unused in SNI). Sampled at reset as MDIX_EN strap; pulldown disables Auto-MDIX. Internal pullup.
42	COL/PHYAD0	bidirectional	MII collision detect output (SNI collision in SNI mode; unused in RMII). Sampled at reset as PHY address bit 0. Internal pullup.
43	RXD_0/PHYAD1	bidirectional	MII/RMII receive data bit 0 (SNI RXD_0). Sampled at reset as PHY address bit 1. Internal pulldown.
44	RXD_1/PHYAD2	bidirectional	MII/RMII receive data bit 1. Sampled at reset as PHY address bit 2. Internal pulldown.
45	RXD_2/PHYAD3	bidirectional	MII receive data bit 2 (unused in RMII/SNI). Sampled at reset as PHY address bit 3. Internal pulldown.
46	RXD_3/PHYAD4	bidirectional	MII receive data bit 3 (unused in RMII/SNI). Sampled at reset as PHY address bit 4. Internal pulldown.
47	IOGND	power_in	I/O ground.
48	IOVDD33	power_in	I/O 3.3 V supply.
49	GNDPAD	power_in	Exposed thermal ground pad on the package underside; must be soldered to the PCB ground plane for thermal and electrical grounding.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	LQFP-48(7x7)
Category	Interface
Pins	49

Ordering variants

Same part, different packaging or reel option.

DP83848IVVX
DP83848IVVXCVV
DP83848IVVXVYB
DP83848IVVXYB

CAD (KiCad official)

Symbol: DP83848IVVX
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (86 pp, sha256 6add7615dee04f2d, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF