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CY7C65642-28LTXCT

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by Ray

Infineon Cypress Semicon USB Converters, QFN-28(5x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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CY7C65642-28LTXCT

Infineon Cypress Semicon · USB Converters · QFN-28(5x5)

CY7C65642-28LTXCT from Infineon Cypress Semicon, in a QFN-28(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D- bidirectional Upstream USB 2.0 D- signal (high/full-speed).
2 D+ bidirectional Upstream USB 2.0 D+ signal (high/full-speed). Internal 1.5 k pull-up integrated.
3 DD-[1] bidirectional Downstream Port 1 USB 2.0 D- signal. Integrated pull-down and series termination.
4 DD+[1] bidirectional Downstream Port 1 USB 2.0 D+ signal. Integrated pull-down and series termination.
5 VCC_A power_in 3.3 V analog power supply to the chip.
6 DD-[2] bidirectional Downstream Port 2 USB 2.0 D- signal. Integrated pull-down and series termination.
7 DD+[2] bidirectional Downstream Port 2 USB 2.0 D+ signal. Integrated pull-down and series termination.
8 RREF passive Bias reference. Connect a 649 ohm precision resistor between RREF and GND.
9 VCC_A power_in 3.3 V analog power supply to the chip.
10 XIN input 12-MHz crystal clock input, or 12-MHz external clock input.
11 XOUT output 12-MHz crystal driver output. Leave NC if an external clock is driving XIN.
12 DD-[3] bidirectional Downstream Port 3 USB 2.0 D- signal. Integrated pull-down and series termination.
13 DD+[3] bidirectional Downstream Port 3 USB 2.0 D+ signal. Integrated pull-down and series termination.
14 VCC_A power_in 3.3 V analog power supply to the chip.
15 DD-[4] bidirectional Downstream Port 4 USB 2.0 D- signal. Integrated pull-down and series termination.
16 DD+[4] bidirectional Downstream Port 4 USB 2.0 D+ signal. Integrated pull-down and series termination.
17 RESET# input Active-LOW external reset input; internal 10 k pull-up. Driving low forces the entire chip to the initial state.
18 TEST/I2C_SCL bidirectional Multiplexed test/I2C clock pin (internal pull-down). Acts as I2C_SCL when an EEPROM is used; logic-high at boot puts the chip in test mode.
19 OVR#[4] input Active-LOW overcurrent detection input for Downstream Port 4. Internal pull-up. Disabled in Gang mode.
20 OVR#[3] input Active-LOW overcurrent detection input for Downstream Port 3. Internal pull-up. Disabled in Gang mode.
21 VCC_D power_in 3.3 V digital power supply to the chip.
22 SELFPWR input Self/bus power select input. 0 = bus-powered, 1 = self-powered.
23 GANG bidirectional Gang/individual power switching mode select and status. Defaults to input after POR: input=1 selects Gang mode (output=0 normal, 1 suspend); input=0 selects Individual mode (output=1 normal, 0 suspend).
24 OVR#[2] input Active-LOW overcurrent detection input for Downstream Port 2. Internal pull-up. Disabled in Gang mode.
25 OVR#[1] input Active-LOW overcurrent detection input for Downstream Port 1. Internal pull-up. Only OVR#[1] is enabled in Gang mode (represents ganged overcurrent).
26 PWR#/I2C_SDA bidirectional Multiplexed power-switch driver output (active-LOW, default) and I2C data pin. Acts as I2C_SDA when an EEPROM is present; otherwise drives an external port power switch.
27 VCC power_in 5 V input to the internal LDO regulator. Leave NC when powering the chip from an external 3.3 V regulator.
28 VREG power_out Internal 5 V-to-3.3 V regulator output (when using internal regulation); also serves as 3.3 V input when using an external regulator.
PAD GND power_in Solderable exposed thermal pad on the underside of the QFN. Sole ground return for the chip; must be soldered to the PCB ground plane.

Key specifications

Parameter Value
Manufacturer Infineon Cypress Semicon
Package QFN-28(5x5)
Category Interface
Pins 29

Ordering variants

Same part, different packaging or reel option.

  • CY7C65642-28LTXCT
  • CY7C65642-28LTXCT48AXC
  • CY7C65642-28LTXCT48AXCT

CAD (KiCad official)

  • Symbol: CY7C65642-28LTXCT
  • Footprint: Package_DFN_QFN:QFN-28-1EP_5x5mm_P0.5mm_EP3.35x3.35mm
  • 3D model: QFN-28(5x5) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Cypress Semicon datasheet (40 pp, sha256 e73715d79d8d5fce, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF