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CJ8850

Changjing · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-89-3L

CJ8850 from Changjing, in a SOT-89-3L. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Device ground / VSS return. All voltages in the datasheet are referenced to this node. Connect directly to the system ground plane and to the ground side of both CIN and COUT with the shortest possible trace.
2 IN power_in Regulator input supply (VIN). Recommended operating range 2.5V to 60V; absolute maximum -0.3V to 65V. Bypass with a ≥1.0μF ceramic capacitor placed as close as possible between IN and GND to avoid start-up voltage transients (a 3Ω series resistor with an X5R MLCC is suggested when the input is hot-plugged).
3 OUT power_out Regulated output (VOUT). Fixed 5.0V nominal for the CJ8850 option, ±2% typical accuracy, up to 150mA continuous (400mA absolute-max IOUT, internal current limit 150-250mA). Bypass with a ≥1.0μF ceramic capacitor to GND (10μF recommended) with appropriate ESR for phase compensation.

Key specifications

Parameter Value
Manufacturer Changjing
Package SOT-89-3L
Category PMIC
Pins 3

CAD (KiCad official)

  • Symbol: CJ8850
  • Footprint: Package_TO_SOT_SMD:SOT-89-3
  • 3D model: SOT-89-3L (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Changjing datasheet (None pp, sha256 c2050774e448f2b1, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

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PCB Footprint

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