component

ch32v203c8t6

Public Unreviewed

by Ray

WCH Jiangsu Qin Heng Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.

componentmcuch32v203c8t6
Overview Files Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Contents

README

markdown

CH32V203C8T6

WCH Jiangsu Qin Heng · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

CH32V203C8T6 from WCH Jiangsu Qin Heng, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup power supply input, 1.8-3.6 V. Powers RTC, external LSE oscillator and backup registers when VDD is off; can be tied to VDD if backup domain isn't used.
2 PC13/TAMPER-RTC bidirectional General-purpose I/O in the backup domain. Default alternate function TAMPER-RTC (intrusion detect / RTC alarm / seconds output). 2 MHz max, 30 pF max load; cannot source current (no LED drive).
3 PC14/OSC32_IN bidirectional General-purpose I/O or LSE 32.768 kHz crystal input (OSC32_IN). Backup-domain pin, 2 MHz max GPIO. When VBAT-only, dedicated to LSE.
4 PC15/OSC32_OUT bidirectional General-purpose I/O or LSE 32.768 kHz crystal output (OSC32_OUT). Backup-domain pin, 2 MHz max GPIO. When VBAT-only, dedicated to LSE.
5 OSC_IN/PD0 bidirectional HSE crystal input (OSC_IN) by default after reset; can be remapped to GPIO PD0. Accepts 3-25 MHz crystal/oscillator.
6 OSC_OUT/PD1 bidirectional HSE crystal output (OSC_OUT) by default after reset; can be remapped to GPIO PD1.
7 NRST input Active-low external reset input (TTL Schmitt). Bidirectional in some MCUs of this family but declared as I here; internal reset pulse ~24-30 ms at power-on.
8 VSSA power_in Analog ground reference for ADC, temperature sensor, PLL, OPA and internal HSI. Tie to VSS at a single point.
9 VDDA power_in Analog supply, 2.4-3.6 V (≥3.0 V if ADC is used; ≥2.4 V required for ADC operation). Must equal VIO/VDD; decouple with 0.1 µF to VSSA.
10 PA0/WKUP bidirectional GPIO PA0, also standby WKUP input, ADC_IN0, TIM2_CH1/ETR, TIM5_CH1 and USART2_CTS alternate functions.
11 PA1 bidirectional GPIO PA1; alt ADC_IN1, TIM2_CH2, TIM5_CH2, USART2_RTS.
12 PA2 bidirectional GPIO PA2; alt ADC_IN2, TIM2_CH3, USART2_TX, OPA2_OUT0.
13 PA3 bidirectional GPIO PA3; alt ADC_IN3, TIM2_CH4, USART2_RX, OPA1_OUT0.
14 PA4 bidirectional GPIO PA4; alt ADC_IN4, SPI1_NSS, USART2_CK, OPA2_OUT1.
15 PA5 bidirectional GPIO PA5; alt ADC_IN5, SPI1_SCK, USART4_TX(remap), OPA2_CH1N.
16 PA6 bidirectional GPIO PA6; alt ADC_IN6, SPI1_MISO, TIM3_CH1, TIM1_BKIN(remap), USART4_CK(remap), OPA1_CH1N.
17 PA7 bidirectional GPIO PA7; alt ADC_IN7, SPI1_MOSI, TIM3_CH2, TIM1_CH1N(remap), USART4_CTS(remap), OPA2_CH1P.
18 PB0 bidirectional GPIO PB0; alt ADC_IN8, TIM3_CH3, TIM1_CH2N(remap), USART4_TX, OPA1_CH1P.
19 PB1 bidirectional GPIO PB1; alt ADC_IN9, TIM3_CH4, TIM1_CH3N(remap), USART4_RX, OPA1_OUT1.
20 PB2/BOOT1 bidirectional GPIO PB2 (FT, 5 V tolerant), also BOOT1 boot-mode select strap sampled at reset. Alternate USART4_CK.
21 PB10 bidirectional GPIO PB10 (FT); alt I2C2_SCL, USART3_TX, TIM2_CH3(remap), OPA2_CH0N.
22 PB11 bidirectional GPIO PB11 (FT); alt I2C2_SDA, USART3_RX, TIM2_CH4(remap), OPA1_CH0N.
23 VSS_1 power_in Digital ground for I/O bank 1. Tie all VSS pins to system ground.
24 VDD_VIO_1 power_in I/O supply for GPIO bank 1, 2.4-3.6 V (3.0-3.6 V if USB used). Must not exceed VDD.
25 PB12 bidirectional GPIO PB12 (FT); alt SPI2_NSS, I2C2_SMBA, USART3_CK, TIM1_BKIN.
26 PB13 bidirectional GPIO PB13 (FT); alt SPI2_SCK, USART3_CTS, TIM1_CH1N.
27 PB14 bidirectional GPIO PB14 (FT); alt SPI2_MISO, USART3_RTS, TIM1_CH2N, OPA2_CH0P.
28 PB15 bidirectional GPIO PB15 (FT); alt SPI2_MOSI, TIM1_CH3N, OPA1_CH0P.
29 PA8 bidirectional GPIO PA8 (FT); alt USART1_CK, TIM1_CH1, MCO (master clock output).
30 PA9 bidirectional GPIO PA9 (FT); alt USART1_TX, TIM1_CH2.
31 PA10 bidirectional GPIO PA10 (FT); alt USART1_RX, TIM1_CH3.
32 PA11/USBDM bidirectional USB2.0 full-speed D− (USBDM) by default; also GPIO PA11 (FT), USART1_CTS, TIM1_CH4, CAN1_RX.
33 PA12/USBDP bidirectional USB2.0 full-speed D+ (USBDP) by default; also GPIO PA12 (FT), USART1_RTS, TIM1_ETR, CAN1_TX.
34 PA13/SWDIO bidirectional 2-wire serial debug data line (SWDIO) after reset; also GPIO PA13 (FT). SDI can be turned off in software to free the pin.
35 VSS_2 power_in Digital ground (bank 2). Tie to VSS.
36 VDD_2 power_in Digital core/IO supply (bank 2), 2.4-3.6 V (3.0-3.6 V for USB).
37 PA14/SWCLK bidirectional 2-wire serial debug clock (SWCLK) after reset; also GPIO PA14 (FT).
38 PA15 bidirectional GPIO PA15 (FT); alt TIM2_CH1/ETR(remap), SPI1_NSS(remap), USART4_RTS(remap).
39 PB3 bidirectional GPIO PB3 (FT); alt TIM2_CH2, USART4_CTS, SPI1_SCK(remap).
40 PB4 bidirectional GPIO PB4 (FT); alt TIM3_CH1(remap), USART4_RTS, SPI1_MISO(remap).
41 PB5 bidirectional GPIO PB5 (FT, NOT 5 V-tolerant on some functions); alt I2C1_SMBA, TIM3_CH2(remap), SPI1_MOSI(remap), USART4_RX(remap).
42 PB6/USBFS_DM bidirectional GPIO PB6 (FT); alt I2C1_SCL, TIM4_CH1, USART1_TX(remap), USBFS_DM (second USB FS host/device D−).
43 PB7/USBFS_DP bidirectional GPIO PB7 (FT); alt I2C1_SDA, TIM4_CH2, USART1_RX(remap), USBFS_DP (second USB FS host/device D+).
44 BOOT0 input Boot-mode select strap sampled at reset; together with BOOT1/PB2 chooses boot source (main Flash / system memory bootloader / SRAM). Should not be left floating.
45 PB8 bidirectional GPIO PB8 (FT); alt TIM4_CH3, I2C1_SCL(remap), CAN1_RX(remap).
46 PB9 bidirectional GPIO PB9 (FT); alt TIM4_CH4, I2C1_SDA(remap), CAN1_TX(remap).
47 VSS_3 power_in Digital ground (bank 3). Tie to VSS.
48 VDD_VIO_3 power_in I/O supply for GPIO bank 3, 2.4-3.6 V (3.0-3.6 V for USB). Must not exceed VDD.

Key specifications

Parameter Value
Manufacturer WCH Jiangsu Qin Heng
Package LQFP-48(7x7)
Category MCU
Pins 48

Ordering variants

  • CH32V203C8T6CxT6
  • CH32V203C8T6C6T6
  • CH32V203C8T6
  • CH32V203C8T6CxU6
  • CH32V203C8T6C6U6
  • CH32V203C8T6C8U6
  • CH32V203C8T6RBT6
  • CH32V203C8T6K8T6
  • CH32V203C8T6G6U6
  • CH32V203C8T6G8R6
  • CH32V203C8T6F6P6
  • CH32V203C8T6F8P6
  • CH32V203C8T6F8U6

CAD (KiCad official)

  • Symbol: CH32V203C8T6
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: WCH Jiangsu Qin Heng datasheet (None pp, sha256 0ef2234f6af69a01, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

Open full view ↗

PCB Footprint

Open full view ↗