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cdcm61002rhbr

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by Ray

Texas Instruments Clock Generators / Frequency Synthesizers / PLL, VQFN-32-EP(5x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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CDCM61002RHBR

Texas Instruments · Clock Generators / Frequency Synthesizers / PLL · VQFN-32-EP(5x5)

CDCM61002RHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC_OUT power_in 3.3-V supply for the output buffers (3.0-3.6 V). Bypass to GND close to the pin.
2 OUTN1 output Universal output channel 1, negative leg. Forms a differential pair with OUTP1 (LVPECL/LVDS) or acts as an independent LVCMOS output depending on OS[1:0].
3 OUTP1 output Universal output channel 1, positive leg. Forms a differential pair with OUTN1 (LVPECL/LVDS) or acts as an independent LVCMOS output depending on OS[1:0].
4 VCC_OUT power_in 3.3-V supply for the output buffers (3.0-3.6 V). Second VCC_OUT pin; bypass to GND close to the pin.
5 OUTN0 output Universal output channel 0, negative leg. Forms a differential pair with OUTP0 (LVPECL/LVDS) or acts as an independent LVCMOS output depending on OS[1:0].
6 OUTP0 output Universal output channel 0, positive leg. Forms a differential pair with OUTN0 (LVPECL/LVDS) or acts as an independent LVCMOS output depending on OS[1:0].
7 CE input Chip Enable control pin (3.3-V LVCMOS). CE=1 places the device in normal operation; CE=0 powers the outputs down (Hi-Z). Internal 150 kΩ pull-up.
8 NC unconnected No connect. Leave floating or tie to GND.
9 VCC_VCO power_in 3.3-V supply for the internal LC-based VCO (3.0-3.6 V). Requires clean bypassing for low phase noise.
10 OS1 input Output type select bit 1 (3.3-V LVCMOS). Together with OS0 selects LVCMOS, LVDS, or LVPECL on the universal outputs and enables/disables OSC_OUT (see Table 6). Internal 150 kΩ pull-up.
11 OS0 input Output type select bit 0 (3.3-V LVCMOS). Together with OS1 selects LVCMOS, LVDS, or LVPECL on the universal outputs and enables/disables OSC_OUT (see Table 6). Internal 150 kΩ pull-up.
12 RSTN input Active-low device reset / PLL recalibration trigger (3.3-V LVCMOS). Must be pulsed low then high after any change to PLL settings. Internal 150 kΩ pull-up.
13 OD0 input Output divider select bit 0 (3.3-V LVCMOS). OD[2:0] selects the shared output divider ratio 1/2/3/4/6/8 (see Table 5). Internal 150 kΩ pull-up.
14 OD1 input Output divider select bit 1 (3.3-V LVCMOS). OD[2:0] selects the shared output divider ratio 1/2/3/4/6/8 (see Table 5). Internal 150 kΩ pull-up.
15 OD2 input Output divider select bit 2 (3.3-V LVCMOS). OD[2:0] selects the shared output divider ratio 1/2/3/4/6/8 (see Table 5). Internal 150 kΩ pull-up.
16 VCC_PLL2 power_in 3.3-V supply for the PLL circuitry (3.0-3.6 V). Requires clean bypassing for low phase noise.
17 REG_CAP2 passive Internal regulator bypass node. Connect a 10-μF Y5V capacitor from this pin to GND; do not drive externally.
18 VCC_PLL1 power_in 3.3-V supply for the PLL circuitry (3.0-3.6 V). Requires clean bypassing for low phase noise.
19 REG_CAP1 passive Internal regulator bypass node. Connect a 10-μF Y5V capacitor from this pin to GND; do not drive externally.
20 VCC_IN power_in 3.3-V supply for the input buffers (3.0-3.6 V). Bypass to GND close to the pin.
21 XIN input Parallel-resonant crystal input, also usable as an LVCMOS reference input. Accepts a 21.875-28.47 MHz fundamental-mode crystal (ESR ≤50 Ω, on-chip load ~8-10 pF) or a single-ended LVCMOS clock.
22 GND1 power_in Additional device ground; internally shorted on-chip to the thermal pad GND. Must be tied to the board ground plane.
23 OSC_OUT output Buffered LVCMOS bypass output of the crystal/input reference (21.875-28.47 MHz). Enabled only when OS[1:0] = 11 per Table 6; otherwise held off.
24 NC unconnected No connect. Leave floating or tie to GND.
25 PR0 input Prescaler/feedback divider select bit 0 (3.3-V LVCMOS). PR[1:0] selects one of four prescaler/feedback pairs (3/24, 5/15, 3/25, 4/20) per Table 4. Internal 150 kΩ pull-up.
26 PR1 input Prescaler/feedback divider select bit 1 (3.3-V LVCMOS). PR[1:0] selects one of four prescaler/feedback pairs (3/24, 5/15, 3/25, 4/20) per Table 4. Internal 150 kΩ pull-up.
27 NC unconnected No connect. Leave floating or tie to GND.
28 NC unconnected No connect. Leave floating or tie to GND.
29 NC unconnected No connect. Leave floating or tie to GND.
30 NC unconnected No connect. Leave floating or tie to GND.
31 NC unconnected No connect. Leave floating or tie to GND.
32 NC unconnected No connect. Leave floating or tie to GND.
33 GND power_in Exposed thermal pad. Must be soldered to the board ground plane; serves as both the primary electrical ground and the primary thermal path (θJP ≈ 4 °C/W with 9 thermal vias).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32-EP(5x5)
Category RTC
Pins 33

Ordering variants

  • CDCM61002RHBR
  • CDCM61002RHBRRHBT

CAD (KiCad official)

  • Symbol: CDCM61002RHBR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (None pp, sha256 dbdb729c3479948f, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

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