component

CDCLVD1204RGTR

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by Ray

Texas Instruments Clock Buffers, Drivers, Distributors, QFN-16-EP(3x3). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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CDCLVD1204RGTR

Texas Instruments · Clock Buffers, Drivers, Distributors · QFN-16-EP(3x3)

CDCLVD1204RGTR from Texas Instruments, in a QFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Device ground.
2 IN_SEL input Input selection with an internal 200-kΩ pullup and pulldown; selects which input port (IN0 or IN1) is routed to the outputs. If left open (mid-level), outputs are disabled (static) for fail-safe operation.
3 INP1 input Positive side of differential clock input pair 1 (redundant input pair or single-ended input). Accepts LVDS, LVPECL, or LVCMOS up to 800 MHz differential.
4 INN1 input Negative side of differential clock input pair 1 (redundant input pair or single-ended input). When used single-ended, VAC_REF must be applied to this pin.
5 VCC power_in 2.5-V supply for the device (recommended range 2.375 V to 2.625 V).
6 INP0 input Positive side of differential clock input pair 0 (redundant input pair or single-ended input). Accepts LVDS, LVPECL, or LVCMOS up to 800 MHz differential.
7 INN0 input Negative side of differential clock input pair 0 (redundant input pair or single-ended input). When used single-ended, VAC_REF must be applied to this pin.
8 VAC_REF output Bias voltage output for capacitive-coupled inputs. TI recommends a 0.1-µF bypass capacitor from this pin to GND. Used to bias the unused negative input pin in single-ended input mode.
9 OUTP0 output Positive side of LVDS differential output pair 0 (ANSI EIA/TIA-644A compatible). Typical
10 OUTN0 output Negative side of LVDS differential output pair 0 (ANSI EIA/TIA-644A compatible).
11 OUTP1 output Positive side of LVDS differential output pair 1 (ANSI EIA/TIA-644A compatible).
12 OUTN1 output Negative side of LVDS differential output pair 1 (ANSI EIA/TIA-644A compatible).
13 OUTP2 output Positive side of LVDS differential output pair 2 (ANSI EIA/TIA-644A compatible).
14 OUTN2 output Negative side of LVDS differential output pair 2 (ANSI EIA/TIA-644A compatible).
15 OUTP3 output Positive side of LVDS differential output pair 3 (ANSI EIA/TIA-644A compatible).
16 OUTN3 output Negative side of LVDS differential output pair 3 (ANSI EIA/TIA-644A compatible).
17 Thermal Pad power_in Exposed thermal pad on the bottom of the VQFN package. Must be soldered to the PCB ground plane for proper thermal and electrical performance.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-16-EP(3x3)
Category Clock/Timing
Pins 17

Ordering variants

Same part, different packaging or reel option.

  • CDCLVD1204RGTR
  • CDCLVD1204RGTRRGTT

CAD (KiCad official)

  • Symbol: CDCLVD1204RGTR
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: QFN-16-EP(3x3) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (28 pp, sha256 1218e131aa4118f0, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF