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CD74HCT174MT

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by Ray

Texas Instruments Flip Flops, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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CD74HCT174MT

Texas Instruments · Flip Flops · SOIC-16

CD74HCT174MT from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MR input Active-low asynchronous master reset. When driven low, all six Q outputs are forced low regardless of clock or data. Requires a minimum pulse width of 20 ns at VCC = 4.5V (HCT).
2 Q0 output Q output of flip-flop 0. Latches the state of D0 on the rising edge of CP; driven low when MR is asserted low. Drives up to 10 LSTTL loads.
3 D0 input Data input to flip-flop 0. Sampled on the low-to-high transition of CP with the specified setup and hold times (tSU = 16 ns min, tH = 5 ns at VCC = 4.5V, HCT).
4 D1 input Data input to flip-flop 1. Sampled on the low-to-high transition of CP with the specified setup and hold times.
5 Q1 output Q output of flip-flop 1. Latches the state of D1 on the rising edge of CP; driven low when MR is asserted low.
6 D2 input Data input to flip-flop 2. Sampled on the low-to-high transition of CP with the specified setup and hold times.
7 Q2 output Q output of flip-flop 2. Latches the state of D2 on the rising edge of CP; driven low when MR is asserted low.
8 GND power_in Ground reference (0 V) for the device. Must be tied to the system ground.
9 CP input Common clock input for all six flip-flops. Data on Dn is transferred to Qn on the low-to-high (rising) transition of CP. Minimum clock pulse width 20 ns; fMAX = 25 MHz at VCC = 4.5V (HCT).
10 Q3 output Q output of flip-flop 3. Latches the state of D3 on the rising edge of CP; driven low when MR is asserted low.
11 D3 input Data input to flip-flop 3. Sampled on the low-to-high transition of CP with the specified setup and hold times.
12 Q4 output Q output of flip-flop 4. Latches the state of D4 on the rising edge of CP; driven low when MR is asserted low.
13 D4 input Data input to flip-flop 4. Sampled on the low-to-high transition of CP with the specified setup and hold times.
14 D5 input Data input to flip-flop 5. Sampled on the low-to-high transition of CP with the specified setup and hold times.
15 Q5 output Q output of flip-flop 5. Latches the state of D5 on the rising edge of CP; driven low when MR is asserted low.
16 VCC power_in Positive supply voltage. HCT operating range 4.5 V to 5.5 V (absolute max 7 V). Bypass with a local 0.1 uF ceramic to GND.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • CD74HCT174MT
  • CD74HCT174MTM
  • CD74HCT174MTM96
  • CD74HCT174MTM96E4
  • CD74HCT174MTE
  • CD74HCT174MTF3A
  • CD74HCT174MTF

CAD (KiCad official)

  • Symbol: CD74HCT174MT
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (None pp, sha256 b04b1439e530ada4, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF