CD74HC4060M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	Q12	output	Counter stage 12 output (divide-by-2^12 = 4096). CMOS/TTL push-pull output; drives ≥10 LSTTL loads. VOH ≥ 4.4 V and VOL ≤ 0.1 V at VCC = 4.5 V under CMOS loads.
2	Q13	output	Counter stage 13 output (divide-by-2^13 = 8192). Bus-driver class output driving ≥15 LSTTL loads.
3	Q14	output	Counter stage 14 output (divide-by-2^14 = 16384). Bus-driver class output driving ≥15 LSTTL loads.
4	Q6	output	Counter stage 6 output (divide-by-2^6 = 64). Standard CMOS output, ≥10 LSTTL loads.
5	Q5	output	Counter stage 5 output (divide-by-2^5 = 32). Standard CMOS output, ≥10 LSTTL loads.
6	Q7	output	Counter stage 7 output (divide-by-2^7 = 128). Standard CMOS output, ≥10 LSTTL loads.
7	Q4	output	Counter stage 4 output (divide-by-2^4 = 16). Standard CMOS output, ≥10 LSTTL loads. Stages Q1-Q3 and Q11 are not brought out to package pins.
8	GND	power_in	Ground reference (0 V). Common return for supply and all I/O.
9	phiO	output	Oscillator output (φO). Buffered output from the internal oscillator section; used as the feedback node for external RC or crystal oscillator networks. Also usable as a buffered clock output at the oscillator frequency.
10	phiO_n	output	Complementary (inverted) oscillator output (φO-bar). Second buffered oscillator tap 180° out of phase with pin 9; typically used with external timing resistor between pins 9/10/11 in RC oscillator configuration.
11	phiI	input	Oscillator input / external clock input (φI). Schmitt-trigger input driving the internal counter through the oscillator stage. When used as an external clock, drive this pin directly; the counter advances on the negative (falling) edge of the buffered signal.
12	MR	input	Master Reset, active high. A high level asynchronously clears all 14 counter stages to zero (all Q outputs low) and disables the oscillator. HCT input loading = 0.35 unit loads.
13	Q9	output	Counter stage 9 output (divide-by-2^9 = 512). Standard CMOS output, ≥10 LSTTL loads.
14	Q8	output	Counter stage 8 output (divide-by-2^8 = 256). Standard CMOS output, ≥10 LSTTL loads.
15	Q10	output	Counter stage 10 output (divide-by-2^10 = 1024). Standard CMOS output, ≥10 LSTTL loads.
16	VCC	power_in	Positive supply. HC types: 2 V to 6 V operation. HCT types: 4.5 V to 5.5 V operation. Absolute maximum −0.5 V to 7 V. Bypass to GND with a local ceramic capacitor.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-16
Category	Logic
Pins	16

Ordering variants

Same part, different packaging or reel option.

CD74HC4060M96M
CD74HC4060M96MT
CD74HC4060M96
CD74HC4060M96E
CD74HC4060M96PW
CD74HC4060M96PWR
CD74HC4060M96PWT
CD74HC4060M96F3A

CAD (KiCad official)

Symbol: CD74HC4060M96
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`cd74hc4060m96.step`	217 KB	You want the bare part, or you mark your own boards.
`cd74hc4060m96-etched.step`	3.1 MB	You want the part with `CD74HC4060M96` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 754 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (20 pp, sha256 1ad52a1a652dc453, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF