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cd74hc165m96

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by Ray

Texas Instruments Shifting Register, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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CD74HC165M96

Texas Instruments · Shifting Register · SOIC-16

CD74HC165M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PL input Parallel Load, active LOW. When PL is LOW, D0-D7 are asynchronously loaded into the register. Must be HIGH for serial shifting.
2 CP input Clock Pulse input. Positive-going (LOW-to-HIGH) transition shifts data one place to the right (Q0→Q1→...→Q7) when PL=HIGH and CE=LOW.
3 D4 input Parallel data input bit 4. Loaded into stage Q4 when PL is asserted LOW.
4 D5 input Parallel data input bit 5. Loaded into stage Q5 when PL is asserted LOW.
5 D6 input Parallel data input bit 6. Loaded into stage Q6 when PL is asserted LOW.
6 D7 input Parallel data input bit 7 (last stage input). Loaded into stage Q7 when PL is asserted LOW.
7 /Q7 output Complementary serial output of the last (Q7) register stage. Provides the inverted value of Q7. Bus-driver output (~15 LSTTL loads).
8 GND power_in Ground reference (0 V). Return for VCC supply and all I/O.
9 Q7 output Serial data output from the last (Q7) register stage. Tie to the DS input of a downstream '165 to cascade for wider parallel-to-serial conversion. Bus-driver output (~15 LSTTL loads).
10 DS input Serial Data input. Sampled at Q0 on the LOW-to-HIGH clock transition while PL=HIGH and CE=LOW.
11 D0 input Parallel data input bit 0 (first stage input). Loaded into stage Q0 when PL is asserted LOW.
12 D1 input Parallel data input bit 1. Loaded into stage Q1 when PL is asserted LOW.
13 D2 input Parallel data input bit 2. Loaded into stage Q2 when PL is asserted LOW.
14 D3 input Parallel data input bit 3. Loaded into stage Q3 when PL is asserted LOW.
15 CE input Clock Enable, active LOW (clock inhibit). When CE=LOW the clock is enabled and shifting occurs on the rising edge of CP. Its LOW-to-HIGH transition should only occur while CP is HIGH for predictable operation.
16 VCC power_in Positive supply voltage. HC types: 2 V to 6 V; HCT types: 4.5 V to 5.5 V. Absolute max 7 V. Decouple locally to GND with a ceramic capacitor.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

Ordering variants

  • CD74HC165M96
  • CD74HC165M96M
  • CD74HC165M96MT
  • CD74HC165M96E
  • CD74HC165M96F3A

CAD (KiCad official)

  • Symbol: CD74HC165M96
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (None pp, sha256 95ae9f075c2701dc, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

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PCB Footprint

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