CD4049UBDR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VCC	power_in	Positive supply voltage pin. Operates at 5V, 10V, or 15V per parametric ratings; absolute maximum VCC to VSS is 20V.
2	G	output	Inverting buffer output 1. G = NOT(A). CMOS output capable of driving two TTL loads with VOL ≤ 0.4V at IOL ≥ 3.3mA.
3	A	input	Logic input 1 to inverter A→G. Input high-level (VIH) may exceed VCC for high-to-low level conversion. Maximum input current 1µA at 18V.
4	H	output	Inverting buffer output 2. H = NOT(B). CMOS output capable of driving two TTL loads.
5	B	input	Logic input 2 to inverter B→H. Input high-level may exceed VCC for level shifting.
6	I	output	Inverting buffer output 3. I = NOT(C). CMOS output capable of driving two TTL loads.
7	C	input	Logic input 3 to inverter C→I. Input high-level may exceed VCC for level shifting.
8	VSS	power_in	Negative supply / ground reference for the device.
9	D	input	Logic input 4 to inverter D→J. Input high-level may exceed VCC for level shifting.
10	J	output	Inverting buffer output 4. J = NOT(D). CMOS output capable of driving two TTL loads.
11	E	input	Logic input 5 to inverter E→K. Input high-level may exceed VCC for level shifting.
12	K	output	Inverting buffer output 5. K = NOT(E). CMOS output capable of driving two TTL loads.
13	NC	unconnected	No internal connection. Leave floating or tie as needed.
14	F	input	Logic input 6 to inverter F→L. Input high-level may exceed VCC for level shifting.
15	L	output	Inverting buffer output 6. L = NOT(F). CMOS output capable of driving two TTL loads.
16	NC	unconnected	No internal connection. Leave floating or tie as needed.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-16
Category	Logic
Pins	16

Ordering variants

Same part, different packaging or reel option.

CD4049UBDRD
CD4049UBDR
CD4049UBDRE
CD4049UBDRDW
CD4049UBDRDWR
CD4049UBDRNS
CD4049UBDRNSR
CD4049UBDRPW
CD4049UBDRPWR

CAD (KiCad official)

Symbol: CD4049UBDR
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`cd4049ubdr.step`	217 KB	You want the bare part, or you mark your own boards.
`cd4049ubdr-etched.step`	2.7 MB	You want the part with `CD4049UBDR` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 663 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (39 pp, sha256 ee56c7e624d98e37, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF