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Pinout
Key specifications
Ordering variants
CAD (KiCad official)
Provenance

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CD4027BPWR

Texas Instruments · Flip Flops · TSSOP-16

CD4027BPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	Q2	output	Non-inverted Q output for flip-flop channel 2. CMOS push-pull output driven from the internal buffered Q latch; standard B-series drive (typ IOH/IOL ≈ 1.3 mA at VDD = 10 V into VOL = 0.5 V / VOH = 9.5 V).
2	Q2#	output	Inverted Q̄ output for flip-flop channel 2. Complementary to Q2, same CMOS buffered drive characteristics as the Q output.
3	CLOCK2	input	Clock input for channel 2. State changes of the flip-flop are synchronous with the positive-going transition of this clock pulse. Minimum clock pulse width 30 ns at VDD = 10 V; maximum toggle frequency 16 MHz typ at 10 V.
4	RESET2	input	Asynchronous Reset input for channel 2. Active-high; forces Q2 low and Q2̄ high independent of the clock. Minimum set/reset pulse width 40 ns at VDD = 10 V.
5	K2	input	K logic input for channel 2. Sampled on the positive clock edge together with J2 to control the flip-flop state (J·K̄ → set, J̄·K → reset, J·K → toggle, J̄·K̄ → hold). CMOS input, IIN ≤ 1 µA at 18 V over full temperature range.
6	J2	input	J logic input for channel 2. Sampled on the positive clock edge with K2 to control the next flip-flop state. CMOS input, standard B-series thresholds (VIL max 3 V, VIH min 7 V at VDD = 10 V).
7	SET2	input	Asynchronous Set input for channel 2. Active-high; forces Q2 high and Q2̄ low independent of the clock. Minimum set pulse width 40 ns at VDD = 10 V.
8	VSS	power_in	Ground / negative supply reference for the device. All input, output, and supply voltages are referenced to this pin.
9	SET1	input	Asynchronous Set input for channel 1. Active-high; forces Q1 high and Q1̄ low independent of the clock. Minimum set pulse width 40 ns at VDD = 10 V.
10	J1	input	J logic input for channel 1. Sampled on the positive clock edge with K1 to determine the next flip-flop state (set/reset/toggle/hold per the J-K truth table).
11	K1	input	K logic input for channel 1. Sampled on the positive clock edge with J1 to control the flip-flop state. CMOS input, IIN ≤ 1 µA at 18 V.
12	RESET1	input	Asynchronous Reset input for channel 1. Active-high; forces Q1 low and Q1̄ high independent of the clock.
13	CLOCK1	input	Clock input for channel 1. Flip-flop state changes occur on the positive-going edge of this signal. Typical toggle rate 16 MHz at VDD = 10 V; clock rise/fall time ≤ 5 µs at 10 V.
14	Q1#	output	Inverted Q̄ output for flip-flop channel 1. Complementary to Q1 with the same CMOS push-pull drive characteristics.
15	Q1	output	Non-inverted Q output for flip-flop channel 1. Standardized symmetrical B-series CMOS drive (source/sink ≈ 1.3 mA at VDD = 10 V).
16	VDD	power_in	Positive supply rail. Recommended operating range 3 V to 18 V (absolute max 20 V) referenced to VSS. Powers both J-K flip-flop channels and their output buffers.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-16
Category	Logic
Pins	16

Ordering variants

CD4027BPWR
CD4027BPWRM
CD4027BPWRM96
CD4027BPWRMT
CD4027BPWRNSR
CD4027BPWRE
CD4027BPWRF3A

CAD (KiCad official)

Symbol: CD4027BPWR
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (None pp, sha256 693dd25443552d73, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

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