component
CD4019BPWR
Public Unreviewedby Ray
Texas Instruments Logic Gates, TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD4019BPWR
Texas Instruments · Logic Gates · TSSOP-16
CD4019BPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | B4 | input | Channel-B data input to the 4th AND/OR select gate. Combined with Kb, contributes the B4·Kb term to output D4. |
| 2 | A3 | input | Channel-A data input to the 3rd AND/OR select gate. Combined with Ka, contributes the A3·Ka term to output D3. |
| 3 | B3 | input | Channel-B data input to the 3rd AND/OR select gate. Combined with Kb, contributes the B3·Kb term to output D3. |
| 4 | A2 | input | Channel-A data input to the 2nd AND/OR select gate. Combined with Ka, contributes the A2·Ka term to output D2. |
| 5 | B2 | input | Channel-B data input to the 2nd AND/OR select gate. Combined with Kb, contributes the B2·Kb term to output D2. |
| 6 | A1 | input | Channel-A data input to the 1st AND/OR select gate. Combined with Ka, contributes the A1·Ka term to output D1. |
| 7 | B1 | input | Channel-B data input to the 1st AND/OR select gate. Combined with Kb, contributes the B1·Kb term to output D1. |
| 8 | VSS | power_in | Negative supply / ground reference. Operating supply (VDD − VSS) range is 3 V to 18 V; absolute maximum 20 V. |
| 9 | Ka | input | Channel-A select control bit. When Ka = 1 the A-channel AND terms (An·Ka) propagate to the Dn outputs; when Ka = Kb = 1 the outputs form the OR (A+B) function. |
| 10 | D1 | output | Select-gate 1 output. D1 = A1·Ka + B1·Kb. |
| 11 | D2 | output | Select-gate 2 output. D2 = A2·Ka + B2·Kb. |
| 12 | D3 | output | Select-gate 3 output. D3 = A3·Ka + B3·Kb. |
| 13 | D4 | output | Select-gate 4 output. D4 = A4·Ka + B4·Kb. |
| 14 | Kb | input | Channel-B select control bit. When Kb = 1 the B-channel AND terms (Bn·Kb) propagate to the Dn outputs; when Ka = Kb = 1 the outputs form the OR (A+B) function. |
| 15 | A4 | input | Channel-A data input to the 4th AND/OR select gate. Combined with Ka, contributes the A4·Ka term to output D4. |
| 16 | VDD | power_in | Positive supply. Operating range 3 V to 18 V referred to VSS; absolute maximum 20 V. Datasheet gives parametric ratings at 5 V, 10 V and 15 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
Ordering variants
Same part, different packaging or reel option.
CD4019BPWRCD4019BPWRECD4019BPWREE4CD4019BPWRFCD4019BPWRF3ACD4019BPWRJM38510/05352BEACD4019BPWRM38510/05352BEACD4019BPWRMCD4019BPWRM96CD4019BPWRMTCD4019BPWRNSR
CAD (KiCad official)
- Symbol:
CD4019BPWR - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (None pp, sha256
88db828df55fcfeb, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).