CD4011BDRG from HANSCHIP semiconductor, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	I1	input	Gate 1, input A. CMOS logic input, VIL max 1.5 V @ VDD=5 V; VIH min 3.5 V @ VDD=5 V. Input leakage ±0.3 µA max @ VDD=15 V.
2	I2	input	Gate 1, input B. CMOS logic input paired with I1 for the first NAND gate producing O1.
3	O1	output	Gate 1 buffered NAND output = NOT(I1 AND I2). VOH ≥ 4.95 V, VOL ≤ 0.05 V @ VDD=5 V,
4	O2	output	Gate 2 buffered NAND output = NOT(I3 AND I4). Same drive characteristics as O1.
5	I3	input	Gate 2, input A. CMOS logic input for the second NAND gate producing O2.
6	I4	input	Gate 2, input B. CMOS logic input paired with I3 for the second NAND gate.
7	VSS	power_in	Ground / negative supply. Reference (0 V) for VDD and all logic signals.
8	I5	input	Gate 3, input A. CMOS logic input for the third NAND gate producing O3.
9	I6	input	Gate 3, input B. CMOS logic input paired with I5 for the third NAND gate.
10	O3	output	Gate 3 buffered NAND output = NOT(I5 AND I6). Same drive characteristics as O1.
11	O4	output	Gate 4 buffered NAND output = NOT(I7 AND I8). Same drive characteristics as O1.
12	I7	input	Gate 4, input A. CMOS logic input for the fourth NAND gate producing O4.
13	I8	input	Gate 4, input B. CMOS logic input paired with I7 for the fourth NAND gate.
14	VDD	power_in	Positive supply, -0.5 V to +18 V absolute max; recommended 3 V to 15 V. Typical IDD = 7.5 µA max @ 5 V, 30 µA max @ 15 V (Tamb=25 °C).

Key specifications

Parameter	Value
Manufacturer	HANSCHIP semiconductor
Package	SOP-14
Category	Logic
Pins	14

Ordering variants

Same part, different packaging or reel option.

CD4011BDRG
CD4011BDRGPG
CD4011BDRGPWRG

CAD (KiCad official)

Symbol: CD4011BDRG
Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
3D model: SOP-14 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`cd4011bdrg.step`	195 KB	You want the bare part, or you mark your own boards.
`cd4011bdrg-etched.step`	2.4 MB	You want the part with `CD4011BDRG` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 601 faces against 237 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: HANSCHIP semiconductor datasheet (10 pp, sha256 ab85323f2c5d5fc1, retrieved 2026-08-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF