CD4007UBM from HGSEMI, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	Q2_PD	passive	Q2 P-channel MOSFET DRAIN terminal. Also serves as the output node when Q2 is used as a complementary inverter (tied with pin 5, Q2 N-drain).
2	Q2_PS	passive	Q2 P-channel MOSFET SOURCE terminal. Typically tied to VDD when Q2 is used as a standard CMOS inverter/gate element.
3	Q2_G	input	Q2 common GATE terminal (both P- and N-channel gates of the Q2 complementary pair are tied together). Used as the input of the Q2 CMOS inverter.
4	Q2_NS	passive	Q2 N-channel MOSFET SOURCE terminal. Typically tied to VSS when Q2 is used as a standard CMOS inverter/gate element.
5	Q2_ND	passive	Q2 N-channel MOSFET DRAIN terminal. Combines with pin 1 (Q2 P-drain) to form the Q2 inverter output node in a typical CMOS configuration.
6	Q1_G	input	Q1 common GATE terminal (both P- and N-channel gates of the Q1 pair). Q1's P-drain and N-source are internally strapped to VDD (pin 14) and VSS (pin 7) respectively, so Q1 is pre-wired as a standalone inverter.
7	VSS	power_in	Negative supply / ground rail. Also the common substrate connection for all N-channel devices (Q1, Q2, Q3 N-substrates) and Q1's N-channel source.
8	Q1_ND	passive	Q1 N-channel MOSFET DRAIN terminal. Combined with pin 13 (Q1 P-source) to expose the Q1 inverter output; when Q1 is used as a fixed inverter this is the low-side of the output.
9	Q3_NS	passive	Q3 N-channel MOSFET SOURCE terminal. Typically tied to VSS when Q3 is used as a standard CMOS inverter/gate element.
10	Q3_G	input	Q3 common GATE terminal (both P- and N-channel gates of the Q3 complementary pair). Used as the input of the Q3 CMOS inverter.
11	Q3_PD	passive	Q3 P-channel MOSFET DRAIN terminal. Available for use as an output node or for building series/parallel MOSFET topologies (NOR/NAND/tree logic).
12	Q3_ND_PS	passive	Common node: Q3 N-channel DRAIN and Q3 P-channel SOURCE tied together internally. Serves as the Q3 inverter output when Q3 is wired as a standard CMOS inverter.
13	Q1_PS	passive	Q1 P-channel MOSFET SOURCE terminal. In the pre-wired 'plus inverter' Q1, this pin is the P-side of the inverter output and is typically tied with pin 8 (Q1 N-drain).
14	VDD	power_in	Positive supply rail (3 V to 15 V recommended, 15 V absolute max). Also the common substrate connection for all P-channel devices (Q1, Q2, Q3 P-substrates) and Q1's P-channel drain.

Key specifications

Parameter	Value
Manufacturer	HGSEMI
Package	SOP-14
Category	Logic
Pins	14

Ordering variants

Same part, different packaging or reel option.

CD4007UBMM/TR
CD4007UBME
CD4007UBMN
CD4007UBMMT/TR

CAD (KiCad official)

Symbol: CD4007UBM
Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
3D model: SOP-14 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: HGSEMI datasheet (13 pp, sha256 284450e1a0d8c60d, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF