CBM706RAS8 from Corebai Microelectronics, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	MR	input	Manual Reset Input (active low). When taken below 0.6 V, an active-low RESET is generated. Internally debounced; an internal 70 uA (typ.) pull-up current holds the input high when floating. Can be driven from TTL/CMOS logic or a bare switch to GND.
2	VCC	power_in	Positive supply input, 2.70 V to 5.5 V operating range (functional down to 1 V for guaranteed RESET). Place a 0.1 uF decoupling capacitor between VCC and GND. Supply current 100 uA typ. at VCC < 3.6 V.
3	GND	power_in	Ground. 0 V reference for all signals. Absolute max sink current 20 mA.
4	PFI	input	Power-Fail Input. Non-inverting input of the internal 1.25 V power-fail comparator. When PFI falls below 1.25 V (typ.), the PFO output is driven low. Tie to GND if unused. Input current +/-25 nA max.
5	PFO	output	Power-Fail Output (active low). Open at PFI >= 1.25 V, driven low when PFI is below the 1.25 V threshold. VOL <= 0.3 V at ISINK = 1.2 mA; VOH >= 0.8 x VCC at ISOURCE = 500 uA (VCC < 3.6 V).
6	WDI	input	Watchdog Input. Each rising or falling edge on WDI clears the internal watchdog timer. If WDI stays static high or low longer than the 1.6 s (typ.) timeout, WDO goes low. Minimum WDI pulse width 100 ns (VCC < 3.6 V) / 50 ns (VCC > 4.5 V). The timer is also cleared whenever reset is asserted.
7	RESET	output	Active-low reset output. Goes low for 200 ms (typ.) when triggered by VCC dropping below the 2.63 V reset threshold or by a low on MR. Stays low while VCC is below threshold and remains valid down to VCC = 1 V (VOL <= 0.3 V at ISINK = 100 uA). A watchdog timeout does not assert RESET unless WDO is externally tied to MR.
8	WDO	output	Watchdog Output (active low). Goes low if the watchdog timer times out due to WDI inactivity, and also whenever VCC is below the reset threshold. Returns high as soon as VCC rises above the reset threshold and the timer is cleared. VOH >= 0.8 x VCC at ISOURCE = 500 uA; VOL <= 0.3 V at ISINK = 500 uA (VCC < 3.6 V).

Key specifications

Parameter	Value
Manufacturer	Corebai Microelectronics
Package	SOP-8
Category	PMIC
Pins	8

Ordering variants

Same part, different packaging or reel option.

CBM706RAS8
CBM706RAS8N8

CAD (KiCad official)

Symbol: CBM706RAS8
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOP-8 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Corebai Microelectronics datasheet (19 pp, sha256 66ae48cae3a68e5f, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF