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README

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CA-IS3642LVW

Chipanalog · Digital Isolators (With Power) · SOIC-16-300mil

CA-IS3642LVW from Chipanalog, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in A-side supply for the internal DC-DC converter primary. Range 3.15 V to 5.5 V (typ 5 V). Decouple to GNDA with 0.1 uF and 10 uF placed within 2 mm of the pin.
2 GNDA power_in A-side ground reference.
3 VI1 input Forward channel 1: A-side logic input driving isolated output VO1 on pin 14. Input thresholds are referenced to VDDL on the LVW variant (VIH >= 2.0 V, VIL <= 0.8 V).
4 VI2 input Forward channel 2: A-side logic input driving isolated output VO2 on pin 13. Referenced to GNDA/VDDL.
5 VO3 output Reverse channel 3: A-side logic output driven by isolated input VI3 on pin 12. Drive strength IOH = -4 mA / IOL = 4 mA at VDDO = 5 V.
6 VO4 output Reverse channel 4: A-side logic output driven by isolated input VI4 on pin 11. Drive strength IOH = -4 mA / IOL = 4 mA at VDDO = 5 V.
7 VDDL power_in A-side logic supply that sets the input-threshold and output logic-high level for VI1/VI2/VO3/VO4. Allows the A-side digital interface to run at a rail different from VDD (2.375 V to 5.5 V). Decouple to GNDA. Present on the LVW/VW-suffix variants (V = VDDL pinout).
8 GNDA power_in Second A-side ground reference; tie to pin 2 (same net).
9 GNDB power_in B-side (isolated) ground reference.
10 SEL input VISO output-voltage select. Tie SEL to VISO (pin 16) for VISO = 5 V; tie to GNDB or leave floating for VISO = 3.3 V. Referenced to GNDB.
11 VI4 input Reverse channel 4: B-side logic input driving isolated output VO4 on pin 6. Referenced to GNDB/VISO.
12 VI3 input Reverse channel 3: B-side logic input driving isolated output VO3 on pin 5. Referenced to GNDB/VISO.
13 VO2 output Forward channel 2: B-side logic output driven by isolated input VI2 on pin 4. Powered from VISO; on loss-of-signal defaults LOW (LVW fail-safe).
14 VO1 output Forward channel 1: B-side logic output driven by isolated input VI1 on pin 3. Powered from VISO; default-low fail-safe on the L-suffix variant.
15 GNDB power_in Second B-side ground reference; tie to pin 9 (same net).
16 VISO power_out Isolated output voltage generated by the internal DC-DC converter (secondary side). Selectable 3.3 V or 5 V via SEL; up to 650 mW output power. Decouple to GNDB with 0.1 uF and 10 uF placed within 2 mm of the pin.

Key specifications

Parameter Value
Manufacturer Chipanalog
Package SOIC-16-300mil
Category Signal Isolation Devices
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • CA-IS3642LVW
  • CA-IS3642LVWHVW
  • CA-IS3642LVWLW
  • CA-IS3642LVWHW

CAD (KiCad official)

  • Symbol: CA-IS3642LVW
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Chipanalog datasheet (39 pp, sha256 74e1e848c9ed7ac2, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF