C8051F020-GQR from SKYWORKS SILICON LABS, in a TQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	TMS	input	JTAG Test Mode Select with internal pull-up.
2	TCK	input	JTAG Test Clock with internal pull-up.
3	TDI	input	JTAG Test Data Input with internal pull-up. Latched on the rising edge of TCK.
4	TDO	tri_state	JTAG Test Data Output with internal pull-up. Data is shifted out on the falling edge of TCK; tri-state driver.
5	/RST	bidirectional	Device Reset. Open-drain output of the internal VDD monitor (drives low when VDD < 2.7 V and MONEN is high). Can be pulled low externally to reset the device.
6	CP1-	input	Comparator 1 inverting analog input.
7	CP1+	input	Comparator 1 non-inverting analog input.
8	CP0-	input	Comparator 0 inverting analog input.
9	CP0+	input	Comparator 0 non-inverting analog input.
10	AGND	power_in	Analog ground. Must be tied to ground.
11	AV+	power_in	Analog supply voltage. Must be tied to +2.7 V to +3.6 V.
12	VREF	bidirectional	Bandgap voltage reference output (all devices). Also DAC voltage reference input on F021/3.
13	AGND	power_in	Analog ground (second AGND pin). Must be tied to ground.
14	AV+	power_in	Analog supply voltage (second AV+ pin). Must be tied to +2.7 V to +3.6 V.
15	VREFD	input	DAC voltage reference input.
16	VREF0	input	ADC0 voltage reference input.
17	VREF1	input	ADC1 voltage reference input.
18	AIN0.0	input	ADC0 input channel 0.
19	AIN0.1	input	ADC0 input channel 1.
20	AIN0.2	input	ADC0 input channel 2.
21	AIN0.3	input	ADC0 input channel 3.
22	AIN0.4	input	ADC0 input channel 4.
23	AIN0.5	input	ADC0 input channel 5.
24	AIN0.6	input	ADC0 input channel 6.
25	AIN0.7	input	ADC0 input channel 7.
26	XTAL1	input	Crystal oscillator input / return for the internal oscillator circuit. Connect a crystal or ceramic resonator between XTAL1 and XTAL2, or drive with an external CMOS clock.
27	XTAL2	output	Crystal oscillator output; excitation driver for a crystal or ceramic resonator.
28	MONEN	input	VDD monitor enable. Tied high enables the internal VDD monitor (forces reset when VDD < 2.7 V); tied low disables the monitor.
29	AIN1.7/A15/P1.7	bidirectional	Muxed: ADC1 input channel 7 (analog) / external memory address bus bit 15 (non-multiplexed mode) / Port 1.7 GPIO. Function selected via the digital crossbar and ADC1 config.
30	AIN1.6/A14/P1.6	bidirectional	Muxed: ADC1 input channel 6 / external memory address bit 14 / Port 1.6 GPIO.
31	AIN1.5/A13/P1.5	bidirectional	Muxed: ADC1 input channel 5 / external memory address bit 13 / Port 1.5 GPIO.
32	AIN1.4/A12/P1.4	bidirectional	Muxed: ADC1 input channel 4 / external memory address bit 12 / Port 1.4 GPIO.
33	AIN1.3/A11/P1.3	bidirectional	Muxed: ADC1 input channel 3 / external memory address bit 11 / Port 1.3 GPIO.
34	AIN1.2/A10/P1.2	bidirectional	Muxed: ADC1 input channel 2 / external memory address bit 10 / Port 1.2 GPIO.
35	AIN1.1/A9/P1.1	bidirectional	Muxed: ADC1 input channel 1 / external memory address bit 9 / Port 1.1 GPIO.
36	AIN1.0/A8/P1.0	bidirectional	Muxed: ADC1 input channel 0 / external memory address bit 8 (non-multiplexed EMI mode) / Port 1.0 GPIO.
37	VDD	power_in	Digital supply voltage. Must be tied to +2.7 V to +3.6 V.
38	DGND	power_in	Digital ground. Must be tied to ground.
39	A15m/A7/P2.7	bidirectional	Muxed: EMI address bit 15 (multiplexed mode) / address bit 7 (non-multiplexed mode) / Port 2.7 GPIO.
40	A14m/A6/P2.6	bidirectional	Muxed: EMI address bit 14 (mux mode) / address bit 6 (non-mux mode) / Port 2.6 GPIO.
41	A13m/A5/P2.5	bidirectional	Muxed: EMI address bit 13 (mux mode) / address bit 5 (non-mux mode) / Port 2.5 GPIO.
42	A12m/A4/P2.4	bidirectional	Muxed: EMI address bit 12 (mux mode) / address bit 4 (non-mux mode) / Port 2.4 GPIO.
43	A11m/A3/P2.3	bidirectional	Muxed: EMI address bit 11 (mux mode) / address bit 3 (non-mux mode) / Port 2.3 GPIO.
44	A10m/A2/P2.2	bidirectional	Muxed: EMI address bit 10 (mux mode) / address bit 2 (non-mux mode) / Port 2.2 GPIO.
45	A9m/A1/P2.1	bidirectional	Muxed: EMI address bit 9 (mux mode) / address bit 1 (non-mux mode) / Port 2.1 GPIO.
46	A8m/A0/P2.0	bidirectional	Muxed: EMI address bit 8 (mux mode) / address bit 0 (non-mux mode) / Port 2.0 GPIO.
47	AD7/D7/P3.7/IE7	bidirectional	Muxed: EMI address/data bit 7 (mux mode) / data bit 7 (non-mux mode) / external interrupt IE7 / Port 3.7 GPIO.
48	AD6/D6/P3.6/IE6	bidirectional	Muxed: EMI address/data bit 6 (mux mode) / data bit 6 (non-mux mode) / external interrupt IE6 / Port 3.6 GPIO.
49	AD5/D5/P3.5	bidirectional	Muxed: EMI address/data bit 5 / data bit 5 / Port 3.5 GPIO.
50	AD4/D4/P3.4	bidirectional	Muxed: EMI address/data bit 4 / data bit 4 / Port 3.4 GPIO.
51	AD3/D3/P3.3	bidirectional	Muxed: EMI address/data bit 3 / data bit 3 / Port 3.3 GPIO.
52	AD2/D2/P3.2	bidirectional	Muxed: EMI address/data bit 2 / data bit 2 / Port 3.2 GPIO.
53	AD1/D1/P3.1	bidirectional	Muxed: EMI address/data bit 1 / data bit 1 / Port 3.1 GPIO.
54	AD0/D0/P3.0	bidirectional	Muxed: EMI address/data bit 0 (multiplexed EMI mode) / data bit 0 (non-multiplexed mode) / Port 3.0 GPIO.
55	/WR/P0.7	bidirectional	Muxed: external memory /WR strobe / Port 0.7 GPIO.
56	/RD/P0.6	bidirectional	Muxed: external memory /RD strobe / Port 0.6 GPIO.
57	ALE/P0.5	bidirectional	Muxed: ALE strobe for external memory address bus (multiplexed EMI mode) / Port 0.5 GPIO.
58	P0.4	bidirectional	Port 0.4 GPIO. Alternate functions (UART, SMBus, SPI, timers, PCA, comparator outputs, etc.) assigned via the priority crossbar.
59	P0.3	bidirectional	Port 0.3 GPIO; crossbar-selectable alternate functions.
60	P0.2	bidirectional	Port 0.2 GPIO; crossbar-selectable alternate functions.
61	P0.1	bidirectional	Port 0.1 GPIO; crossbar-selectable alternate functions.
62	P0.0	bidirectional	Port 0.0 GPIO; crossbar-selectable alternate functions.
63	DGND	power_in	Digital ground.
64	VDD	power_in	Digital supply voltage (+2.7 V to +3.6 V).
65	AD7/D7/P7.7	bidirectional	Muxed: EMI address/data bit 7 / data bit 7 / Port 7.7 GPIO.
66	AD6/D6/P7.6	bidirectional	Muxed: EMI address/data bit 6 / data bit 6 / Port 7.6 GPIO.
67	AD5/D5/P7.5	bidirectional	Muxed: EMI address/data bit 5 / data bit 5 / Port 7.5 GPIO.
68	AD4/D4/P7.4	bidirectional	Muxed: EMI address/data bit 4 / data bit 4 / Port 7.4 GPIO.
69	AD3/D3/P7.3	bidirectional	Muxed: EMI address/data bit 3 / data bit 3 / Port 7.3 GPIO.
70	AD2/D2/P7.2	bidirectional	Muxed: EMI address/data bit 2 / data bit 2 / Port 7.2 GPIO.
71	AD1/D1/P7.1	bidirectional	Muxed: EMI address/data bit 1 / data bit 1 / Port 7.1 GPIO.
72	AD0/D0/P7.0	bidirectional	Muxed: EMI address/data bit 0 (mux mode) / data bit 0 (non-mux mode) / Port 7.0 GPIO.
73	A15m/A7/P6.7	bidirectional	Muxed: EMI address bit 15 (mux mode) / address bit 7 (non-mux mode) / Port 6.7 GPIO.
74	A14m/A6/P6.6	bidirectional	Muxed: EMI address bit 14 / address bit 6 / Port 6.6 GPIO.
75	A13m/A5/P6.5	bidirectional	Muxed: EMI address bit 13 / address bit 5 / Port 6.5 GPIO.
76	A12m/A4/P6.4	bidirectional	Muxed: EMI address bit 12 / address bit 4 / Port 6.4 GPIO.
77	A11m/A3/P6.3	bidirectional	Muxed: EMI address bit 11 / address bit 3 / Port 6.3 GPIO.
78	A10m/A2/P6.2	bidirectional	Muxed: EMI address bit 10 / address bit 2 / Port 6.2 GPIO.
79	A9m/A1/P6.1	bidirectional	Muxed: EMI address bit 9 / address bit 1 / Port 6.1 GPIO.
80	A8m/A0/P6.0	bidirectional	Muxed: EMI address bit 8 (mux mode) / address bit 0 (non-mux mode) / Port 6.0 GPIO.
81	A15/P5.7	bidirectional	Muxed: EMI address bit 15 (non-mux mode) / Port 5.7 GPIO.
82	A14/P5.6	bidirectional	Muxed: EMI address bit 14 (non-mux mode) / Port 5.6 GPIO.
83	A13/P5.5	bidirectional	Muxed: EMI address bit 13 (non-mux mode) / Port 5.5 GPIO.
84	A12/P5.4	bidirectional	Muxed: EMI address bit 12 (non-mux mode) / Port 5.4 GPIO.
85	A11/P5.3	bidirectional	Muxed: EMI address bit 11 (non-mux mode) / Port 5.3 GPIO.
86	A10/P5.2	bidirectional	Muxed: EMI address bit 10 (non-mux mode) / Port 5.2 GPIO.
87	A9/P5.1	bidirectional	Muxed: EMI address bit 9 (non-mux mode) / Port 5.1 GPIO.
88	A8/P5.0	bidirectional	Muxed: EMI address bit 8 (non-mux mode) / Port 5.0 GPIO.
89	DGND	power_in	Digital ground.
90	VDD	power_in	Digital supply voltage (+2.7 V to +3.6 V).
91	/WR/P4.7	bidirectional	Muxed: external memory /WR strobe / Port 4.7 GPIO.
92	/RD/P4.6	bidirectional	Muxed: external memory /RD strobe / Port 4.6 GPIO.
93	ALE/P4.5	bidirectional	Muxed: ALE strobe for external memory address bus (multiplexed EMI mode) / Port 4.5 GPIO.
94	P4.4	bidirectional	Port 4.4 GPIO.
95	P4.3	bidirectional	Port 4.3 GPIO.
96	P4.2	bidirectional	Port 4.2 GPIO.
97	P4.1	bidirectional	Port 4.1 GPIO.
98	P4.0	bidirectional	Port 4.0 GPIO.
99	DAC1	output	Digital-to-analog converter 1 voltage output.
100	DAC0	output	Digital-to-analog converter 0 voltage output.

Key specifications

Parameter	Value
Manufacturer	SKYWORKS SILICON LABS
Package	TQFP-100(14x14)
Category	MCU
Pins	100

Ordering variants

Same part, different packaging or reel option.

C8051F020-GQR

CAD (KiCad official)

Symbol: C8051F020-GQR
Footprint: Package_QFP:TQFP-100_14x14mm_P0.5mm
3D model: TQFP-100(14x14) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: SKYWORKS SILICON LABS datasheet (272 pp, sha256 775b036ec3562044, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF