BQ76200PWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDDCP	power_out	Charge pump output. Connect a capacitor (typ 470 nF) to BAT. Do not load this pin. Charge pump voltage V(VDDCP)-V(BAT) is typically 12 V (9 V-14 V).
2	BAT	power_in	Top of battery stack. Battery cell input supply pin; recommended operating range 8 V to 75 V (100 V absolute max).
3	NC	unconnected	No connect. Leave the pin floating.
4	CHG_EN	input	Charge FET enable. Digital input from AFE or MCU (VIL max 0.6 V, VIH min 1.2 V, 15 V absolute max). Internal ~1 MΩ pull-down. Must be current limited (max 5 mA).
5	CP_EN	input	Charge pump enable. Internally logic-ORed with CHG_EN and DSG_EN signals. Digital input (VIL max 0.6 V, VIH min 1.2 V, 15 V absolute max) with internal ~1 MΩ pull-down.
6	DSG_EN	input	Discharge FET enable. Digital input (VIL max 0.6 V, VIH min 1.2 V, 15 V absolute max) with internal ~1 MΩ pull-down.
7	PMON_EN	input	Pack monitor enable. Enables the internal switch (typ 2.5 kΩ, 1.5-3.5 kΩ) between PACK and PACKDIV pins to allow pack-voltage sensing. Recommended to tie to ground if unused.
8	PCHG_EN	input	Precharge FET enable. Digital input controlling the P-channel precharge FET driver. Recommended to tie to ground if unused.
9	VSS	power_in	Ground reference.
10	PACKDIV	output	PACK voltage after internal switch. Connect to MCU ADC via an external resistor divider to sense the pack voltage when PMON_EN is high. Leave floating if unused.
11	PACK	power_in	Analog input from the PACK+ terminal. Charger/load voltage input; recommended range 0 V to 75 V (100 V absolute max).
12	DSG	output	Gate drive for discharge N-channel high-side FET. Gate drive voltage V(DSG)-V(PACK) typically 12 V (9-14 V) when DSG_EN=Hi. Driver on-resistance 3.5 kΩ typ; off-resistance 1 kΩ typ.
13	NC	unconnected	No connect. Leave the pin floating.
14	PCHG	output	Gate drive for precharge P-channel FET. Provides current-limited pre-charge of significantly depleted cell packs. Gate drive V(PACK)-V(PCHG) typically 12 V (5-14 V) when V(PACK)>17 V and V(BAT)<V(PACK). Leave floating if unused.
15	NC	unconnected	No connect. Leave the pin floating.
16	CHG	output	Gate drive for charge N-channel high-side FET. Gate drive voltage V(CHG)-V(BAT) typically 12 V (9-14 V) when CHG_EN=Hi. Driver on-resistance 1.1 kΩ typ; off-resistance 0.3 kΩ typ.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-16
Category	PMIC
Pins	16

Ordering variants

Same part, different packaging or reel option.

BQ76200PWR

CAD (KiCad official)

Symbol: BQ76200PWR
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`bq76200pwr.step`	205 KB	You want the bare part, or you mark your own boards.
`bq76200pwr-etched.step`	2.7 MB	You want the part with `BQ76200PWR` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 665 faces against 255 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (30 pp, sha256 fb2ebcf8e875aa0a, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF