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Contents

Pinout
Key specifications
Ordering variants
CAD (KiCad official)
3D model downloads
Provenance

README

markdown

BQ25703ARSNR

Texas Instruments · Battery Management · VQFN-32-EP(4x4)

BQ25703ARSNR from Texas Instruments, in a VQFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VBUS	power_in	Charger input voltage (0 to 24 V operating). An input low-pass filter of 1Ω and 0.47 µF (minimum) is recommended.
2	ACN	input	Input current sense resistor negative input. Leakage on ACP/ACN are matched. Series resistors on ACP and ACN pins are placed between sense resistor and filter cap.
3	ACP	input	Input current sense resistor positive input. Leakage on ACP/ACN are matched.
4	CHRG_OK	output	Open-drain active-high indicator that a good power source is connected to the charger input. Pull up to a rail with a 10-kΩ resistor. HIGH when VBUS rises above 3.5V or falls below 24.5V after 50ms deglitch; LOW when VBUS falls below 3.2V or rises above 26V.
5	EN_OTG	input	Active HIGH input to enable OTG mode. When EN_OTG is HIGH and REG0x35[4] is HIGH, OTG can be enabled.
6	ILIM_HIZ	input	Input current limit input. Program ILIM_HIZ voltage via a resistor divider from supply rail to ground: V(ILIM_HIZ) = 1V + 40 × IDPM × RAC. Below 0.4 V the device enters Hi-Z; above 0.8 V normal operation.
7	VDDA	power_in	Internal reference bias pin. Connect a 10-Ω resistor from REGN to VDDA and a 1-µF ceramic capacitor from VDDA to power ground.
8	IADPT	output	Buffered adapter current output. V(IADPT) = 20 or 40 × (V(ACP) − V(ACN)), ratio selectable in REG0x00[4]. Place resistor to ground for inductor value (137 kΩ for 2.2 µH). Output clamped below 3.3 V.
9	IBAT	output	Buffered battery current output selected by I2C. V(IBAT) = 8 or 16 × (V(SRP) − V(SRN)) for charge current, or 8 or 16 × (V(SRN) − V(SRP)) for discharge current, with ratio in REG0x00[3]. Output clamped below 3.3 V; may float if unused.
10	PSYS	output	Current-mode system power monitor. Output current proportional to total power from adapter and battery, gain selectable via I2C. Place resistor from PSYS to ground to generate output voltage. Output clamped below 3.3 V.
11	PROCHOT	output	Active-low open-drain processor-hot indicator output. Monitors adapter input current, battery discharge current and system voltage. Asserts a minimum 10-ms pulse (width adjustable in REG0x36[5:2]) after any event in the PROCHOT profile.
12	SDA	bidirectional	I2C open-drain data I/O. Connect to data line from host controller or smart battery. Connect a 10-kΩ pullup resistor per I2C specifications.
13	SCL	input	I2C clock input. Connect to clock line from host controller or smart battery. Connect a 10-kΩ pullup resistor per I2C specifications.
14	CMPIN	input	Input of independent comparator; compares voltage sensed on CMPIN to an internal reference. Polarity, output polarity and deglitch time selectable via I2C. With polarity HIGH (REG0x30[6]=1) place resistor between CMPIN and CMPOUT for hysteresis programming; with polarity LOW internal hysteresis is 100 mV. Tie to ground if unused.
15	CMPOUT	output	Open-drain output of independent comparator. Place pullup resistor from CMPOUT to pullup supply rail. Internal reference, output polarity and deglitch time are selectable by I2C.
16	COMP1	passive	Buck-boost converter compensation pin 1. Refer to bq25700 EVM schematic for COMP1 RC network.
17	COMP2	passive	Buck-boost converter compensation pin 2. Refer to bq25700 EVM schematic for COMP2 RC network.
18	CELL_BATPRESZ	input	Battery cell-count selection and battery-presence pin for 1- to 4-cell settings. Biased from VDDA. Also sets SYSOVP threshold (5 V for 1-cell, 12 V for 2-cell, 18.5 V for 3-cell). Pulled below V(CELL_BATPRESZ_FALL) indicates battery removal; the device exits LEARN mode and disables charge.
19	SRN	input	Charge current sense resistor negative input. Also used for battery voltage sensing. Connect optional 0.1-µF ceramic capacitor to GND for common-mode filtering; connect 0.1-µF between SRP and SRN for differential-mode filtering. 10-Ω series resistors are placed on SRP/SRN for reverse-battery protection.
20	SRP	input	Charge current sense resistor positive input. Connect 0.1-µF ceramic capacitor from SRP to SRN for differential-mode filtering. Optional 0.1-µF to GND for common-mode filtering. 10-Ω series resistors for reverse-battery protection.
21	BATDRV	output	P-channel battery FET (BATFET) gate driver output. Shorted to VSYS to turn OFF BATFET; 10 V below VSYS to fully turn ON BATFET. In linear mode regulates VSYS at minimum system voltage when battery is depleted. Fully ON during fast charge and supplement mode.
22	VSYS	power_in	Charger system voltage sensing. The system voltage regulation limit is programmed in REG0x05/04() and REG0x0D/0C().
23	SW2	power_in	Boost mode high-side power MOSFET driver source. Connect to the source of the high-side n-channel MOSFET (Q4).
24	HIDRV2	output	Boost mode high-side power MOSFET (Q4) driver. Connect to high-side n-channel MOSFET gate.
25	BTST2	power_in	Boost mode high-side power MOSFET driver power supply. Connect a 0.047-µF capacitor between SW2 and BTST2. Bootstrap diode between REGN and BTST2 is integrated.
26	LODRV2	output	Boost mode low-side power MOSFET (Q3) driver. Connect to low-side n-channel MOSFET gate.
27	PGND	power_in	Device power ground.
28	REGN	power_out	6-V linear regulator output supplied from VBUS or VSYS. LDO is active when VBUS is above V(VBUS_CONVEN). Connect a 2.2- or 3.3-µF ceramic capacitor from REGN to power ground. REGN output is for the power-stage gate drive.
29	LODRV1	output	Buck mode low-side power MOSFET (Q2) driver. Connect to low-side n-channel MOSFET gate.
30	BTST1	power_in	Buck mode high-side power MOSFET driver power supply. Connect a 0.047-µF capacitor between SW1 and BTST1. Bootstrap diode between REGN and BTST1 is integrated.
31	HIDRV1	output	Buck mode high-side power MOSFET (Q1) driver. Connect to high-side n-channel MOSFET gate.
32	SW1	power_in	Buck mode high-side power MOSFET driver source. Connect to the source of the high-side n-channel MOSFET (Q1).
33	PAD	power_in	Exposed thermal pad beneath the IC. Analog ground and power ground star-connected near the IC's ground. Always solder to board with vias to power-ground planes for both grounding and thermal dissipation.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-32-EP(4x4)
Category	PMIC
Pins	33

Ordering variants

BQ25703ARSNR
BQ25703ARSNRRSNT

CAD (KiCad official)

Symbol: BQ25703ARSNR
Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
3D model: VQFN-32-EP(4x4) (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`bq25703arsnr.step`	76 KB	You want the bare part, or you mark your own boards.
`bq25703arsnr-etched.step`	2.2 MB	You want the part with `BQ25703ARSNR` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 540 faces against 72 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (86 pp, sha256 04595bdc24718c28, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF