BQ24296MRGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VBUS	power_in	Charger input voltage. Internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID with VBUS on source. Place a 1-uF ceramic capacitor from VBUS to PGND close to IC. VBUS operating range 3.9-6.2 V (abs max 15 V).
2	PSEL	input	Power source selection input. High indicates a USB host source, Low indicates an adapter source.
3	PG	output	Open-drain active-low power good indicator. Connect to the pull-up rail via a 10-kOhm resistor. LOW indicates a good input source if the input voltage is between UVLO and ACOV, above SLEEP mode threshold, and current limit is above 30 mA.
4	STAT	output	Open-drain charge status output to indicate various charger operations. Connect to the pull-up rail via a 10-kOhm resistor. LOW = charge in progress, HIGH = charge complete or charge disabled. Blinks at 1 Hz on fault.
5	SCL	input	I2C interface clock. Connect SCL to the logic rail through a 10-kOhm pull-up resistor.
6	SDA	bidirectional	I2C interface data. Connect SDA to the logic rail through a 10-kOhm pull-up resistor.
7	INT	output	Open-drain interrupt output. Connect INT to a logic rail via a 10-kOhm resistor. Sends active-low 256-us pulse to host to report charger device status and fault.
8	OTG	input	USB current limit selection pin in buck mode, and active-high enable pin during boost (OTG) mode. In buck mode with USB host (PSEL=High): OTG=High -> IIN limit 500 mA; OTG=Low -> IIN limit 100 mA. Boost mode activated when REG01[5]=1.
9	CE	input	Active-low Charge Enable pin. Battery charging is enabled when REG01[5:4] = 01 and CE = Low. CE pin must be pulled high or low.
10	ILIM	input	ILIM sets the maximum input current limit by regulating the ILIM voltage at 1 V. A resistor connected from ILIM to GND sets IINMAX = (1V/RILIM) x KILIM. Actual input current limit is the lower of ILIM and REG00[2:0]. Minimum programmed limit is 500 mA.
11	TS	input	Temperature qualification voltage input. Connect an NTC thermistor via resistor divider from REGN to TS to GND. Charge suspends or boost disables when TS is out of range. 103AT-2 thermistor recommended.
12	QON	input	BATFET enable control in shipping mode. Low-to-high transition (min 2 ms high level) turns on BATFET to exit shipping mode. Internal 1-MOhm pull-down. If not used, may be NC or tied to TS pin (10k NTC thermistor only).
13	BAT	power_in	Battery connection point to the positive pin of the battery pack. The internal BATFET is connected between BAT and SYS. Connect a 10-uF capacitor close to the BAT pin.
14	BAT	power_in	Battery connection point (parallel with pin 13) to the positive pin of the battery pack. The internal BATFET is connected between BAT and SYS.
15	SYS	power_out	System connection point. The internal BATFET is connected between BAT and SYS. When the battery falls below the minimum system voltage, the switch-mode converter keeps SYS above the minimum system voltage. Max ~4.43 V, min programmable 3.5 V.
16	SYS	power_out	System connection point (parallel with pin 15). Switch-mode converter output; feeds system rail.
17	PGND	power_in	Power ground connection for high-current power converter node. Internally connected to the source of the n-channel LSFET. Connect directly to ground connection of input and output capacitors. Star-connect PGND to analog GND near IC.
18	PGND	power_in	Power ground connection (parallel with pin 17). Source of internal n-channel LSFET.
19	SW	output	Switching node connecting to output inductor. Internally SW is connected to the source of the n-channel HSFET and the drain of the n-channel LSFET. Connect a 0.047-uF bootstrap capacitor from SW to BTST.
20	SW	output	Switching node (parallel with pin 19) connecting to output inductor.
21	BTST	passive	PWM high-side driver positive supply (bootstrap). Internally BTST is connected to the anode of the boot-strap diode. Connect a 0.047-uF bootstrap capacitor from SW to BTST.
22	REGN	power_out	PWM low-side driver positive supply output (internal LDO). Internally REGN is connected to the cathode of the boot-strap diode. Connect a 4.7-uF (10-V) ceramic capacitor from REGN to analog GND. Also serves as bias rail of TS pin.
23	PMID	power_out	Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET. Connect a 1-uF capacitor on VBUS to PGND and 8.2-uF or more on PMID to PGND.
24	VBUS	power_in	Charger input voltage (parallel with pin 1). Internal RBFET connected between VBUS and PMID.
PAD	Thermal Pad	power_in	Exposed thermal pad beneath the IC for heat dissipation. Always solder thermal pad to the board, and have vias on the thermal pad plane star-connecting to PGND and ground plane for high-current power converter.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-24-EP(4x4)
Category	PMIC
Pins	25

Ordering variants

BQ24296MRGER
BQ24296MRGERRGET

CAD (KiCad official)

Symbol: BQ24296MRGER
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (52 pp, sha256 8fd83e8f2362be7c, retrieved 2026-08-17, tier: manufacturer)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF