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bq24103arhlr

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Texas Instruments Battery Management, QFN-20-EP(3.7x4.7). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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BQ24103ARHLR

Texas Instruments · Battery Management · QFN-20-EP(3.7x4.7)

BQ24103ARHLR from Texas Instruments, in a QFN-20-EP(3.7x4.7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT power_out Charge current output / inductor connection (paired with pin 20). Connect the switching inductor here; add an external Zener/TVS (e.g. MMBZ18VALT1) to PGND to clamp voltage spikes and protect the integrated power MOSFETs during abnormal conditions.
2 STAT1 output Charge status 1, open-drain output (10 mA max sink). Turns on to indicate charge-in-progress. Combined with STAT2 it encodes charger state (see Table 1). Typically drives a status LED with a 1.5 kΩ pull-up.
3 IN power_in Charger input voltage (paired with pin 4). Connect adapter/DC input here; 20 V absolute-max, 4.35 V to 16 V recommended operating range. Both IN pins must be tied together and to VCC through the input filter.
4 IN power_in Charger input voltage (paired with pin 3). Both IN pins are internally connected; tie together to the adapter rail with input bulk/bypass capacitance.
5 PG output Power-good status, open-drain output (10 mA max sink). Pulls low when a valid VCC is detected; released (high-Z) in sleep mode. Can drive an LED or a host processor input via a pull-up (typ. 1.5 kΩ to VTSB or a logic rail).
6 VCC power_in Analog device supply input. Tie to IN through the input filter; requires a 0.1 µF bypass capacitor to VSS. 4.35 V to 16 V recommended, 20 V absolute-max.
7 TTC input Timer and termination control. Connect a capacitor from this pin to GND to set the safety-timer period. Driving this pin low disables the safety timer and charge-termination detection. 7 V absolute-max input rating.
8 ISET1 bidirectional Fast-charge current set point. Connect a resistor from this pin to GND to program the fast-charge current; IREG ≈ (V(ISET1)/R(ISET1)) × K. 3.3 V absolute-max input rating.
9 ISET2 bidirectional Precharge and termination current set point. Set by a resistor to ground. A low-level CMODE signal (system-controlled variants) selects ISET2 rate; when the battery reaches the regulation set point the part switches to voltage regulation regardless of CMODE. 3.3 V absolute-max input rating.
10 VSS power_in Analog ground. Must be connected to ground at all times. The exposed thermal pad is internally connected to VSS.
11 VTSB power_out TS internal bias-regulator output. Connect a 0.1 µF to 1 µF ceramic capacitor from this pin to VSS. Used to power the NTC thermistor divider on the TS pin (and optionally the STAT/PG LED pull-ups). 3.6 V absolute-max.
12 TS input Battery-temperature sense input. Its voltage is compared against internal thresholds to gate charging. Drive with an NTC thermistor (e.g. 103AT) plus a voltage divider powered from VTSB (see Figure 10). 7 V absolute-max input rating.
13 CELLS input Cell-count select (available on fixed-output variants including bq24103A). Ground or float this pin for single-cell (4.2 V) operation; pull up to VCC through a resistor for two-cell (8.4 V) operation. 20 V absolute-max input rating.
14 BAT input Battery-voltage sense input. Connect directly to the battery-pack positive terminal (after the sense resistor). Bypass with a 0.1 µF capacitor to PGND if the leads to the battery are long/inductive. 20 V absolute-max.
15 SNS input Charge current-sense input. Battery current is sensed via the voltage drop across an external sense resistor (typ. 0.1 Ω) in series with the battery pack between SNS and BAT. Requires a 0.1 µF capacitor to PGND.
16 CE input Charger enable input, active-low. Drive high to suspend charging and place the device in low-power sleep mode; drive low (or leave low) to enable charging. Do NOT pull up this input to VTSB. 20 V absolute-max input rating.
17 PGND power_in Power ground return for the integrated power FETs (paired with pin 18). Route with heavy copper to the input/output capacitor ground; may share a plane with VSS.
18 PGND power_in Power ground return for the integrated power FETs (paired with pin 17). Tie both PGND pins together on the board.
19 STAT2 output Charge status 2, open-drain output (10 mA max sink). Turns on to indicate charge-done; combined with STAT1 encodes charger state (see Table 1). Typically drives a status LED via a 1.5 kΩ pull-up.
20 OUT power_out Charge current output / inductor connection (paired with pin 1). Both OUT pins are internally connected and must both be routed to the output inductor. -0.7 V to 20 V absolute-max.
21 PAD power_in Exposed thermal pad on the underside of the RHL package. Internally connected to VSS; must be soldered to a copper pad at the same potential as VSS and stitched to the ground plane with a 2×3 via matrix for thermal performance. Can serve as the star ground between VSS and PGND.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-20-EP(3.7x4.7)
Category PMIC
Pins 21

Ordering variants

  • BQ24103ARHLR
  • BQ24103ARHLRRHLT

CAD (KiCad official)

  • Symbol: BQ24103ARHLR
  • Footprint: Package_DFN_QFN:QFN-20-1EP_4x5mm_P0.5mm_EP2.65x3.65mm
  • 3D model: QFN-20-EP(3.7x4.7) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (None pp, sha256 ffe9c663243fa4d1, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

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