BL0972 from BL Shanghai Belling, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VP	input	Voltage-channel differential input, positive side. Max differential input +/-0.6 V at 1x PGA gain (approx +/-37.5 mV at 16x). Referenced to VN.
2	RST	input	Active-low chip reset. Held high through a pull-up in reference designs; asserted low to reinitialize the IC.
3	AGND	power_in	Analog ground return. Should be routed separately from the current-sense return per PCB layout guidance.
4	DGND	power_in	Digital ground return for the SPI and control logic.
5	CS	input	SPI chip-select input, active low. Frames each SPI transaction to the host MCU.
6	DOUT	output	SPI serial data out (MISO). Drives register read data back to the host.
7	DIN	input	SPI serial data in (MOSI). Receives command/address/data words from the host.
8	SCLK	input	SPI serial clock input. Full timing specification is in the standalone datasheet (BL0972_Datasheet_Vx.x.pdf).
9	IRQ	output	Interrupt/status output. Reference designs drive a status LED via a 1.2 k series resistor.
10	VPP	passive	VPP factory/test pin. Brought out to a header in reference designs; not used in normal operation.
11	CF	output	Energy calibration pulse output. Configurable through MODE3 register; frequency scales with active power (CF_CNT counter). Reference boards route it to an LED indicator.
12	MF	output	Multi-function output, default function is overcurrent alarm (fast-RMS threshold). Alternate roles are selected through the MODE3 register.
13	DVDD18	power_out	Internal 1.8 V digital LDO output. Requires an external decoupling capacitor (0.1 uF) placed close to the pin; do NOT drive externally.
14	VDD	power_in	Main 3.3 V supply input. Decoupled with a local 0.1 uF placed close to the pin per the PCB layout guidance.
15	AGND	power_in	Analog ground return (second AGND pin).
16	IN	input	Current-channel differential input, negative side. Paired with IP; supports 1/2/8/16x PGA (16x gives approx +/-37.5 mV max differential).
17	IP	input	Current-channel differential input, positive side. Route with IN as a tight differential pair to the shunt or CT burden network.
18	VT	passive	Auxiliary analog pin (VT). In the AC reference design it is tied via an STV312-class device to GND; used for internal biasing/test.
19	Vref	power_out	Internal 1.097 V ADC voltage reference output. Requires an external 0.1 uF decoupling capacitor to AGND close to the pin.
20	VN	input	Voltage-channel differential input, negative side. Paired with VP.

Key specifications

Parameter	Value
Manufacturer	BL Shanghai Belling
Package	TSSOP-20
Category	Data Acquisition
Pins	20

CAD (KiCad official)

Symbol: BL0972
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: BL Shanghai Belling datasheet (10 pp, sha256 69d699ccb472717e, retrieved 2026-08-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF