BISS0001DRG from HANSCHIP semiconductor, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	A	input	Trigger mode control input. A='1' enables repeatable triggering; A='0' selects non-repeatable trigger mode. VAH >= 3.5 V, VAL <= 1.5 V at VDD=5V.
2	VO	output	Control signal output. Driven high on a valid trigger (VS rising edge) and remains high for the delay time Tx; otherwise low. VOH >= 4 V, VOL <= 0.4 V at VDD=5V.
3	RR1	passive	Output delay time Tx adjustment pin. External resistor R1 to RC1/capacitor C1 sets Tx ≈ 67025 * R1 * C1.
4	RC1	passive	Output delay time Tx adjustment pin. Works with RR1 and external RC network to set delay period Tx.
5	RC2	passive	Trigger blocking time Ti adjustment pin. External RC with RR2 sets Ti ≈ 60 * R2 * C2.
6	RR2	passive	Trigger blocking time Ti adjustment pin. Works with RC2 to set the blocking period after Tx expires.
7	VSS	power_in	Negative supply / ground. Typically tied to 0 V.
8	VRF/RESET	input	Reference voltage and reset input. Normally tied to VDD; driving this pin to '0' resets the internal timers.
9	VC	input	Trigger inhibit input. Triggering is inhibited when VC < VR (~0.2*VDD) and enabled when VC > VR. Commonly driven by a CdS photocell for ambient-light gating.
10	IB	passive	Op-amp bias current setting pin. Connect an external resistor RB (~1 MΩ) from IB to VSS to set the internal op-amp bias.
11	VDD	power_in	Positive supply input. Operating range 3.0 to 5.0 V; absolute maximum +6 V.
12	2OUT	output	Second-stage internal op-amp (OP2) output. Feeds the bidirectional amplitude discriminator (COP1/COP2).
13	2IN-	input	Second-stage op-amp (OP2) inverting input. Typically connected to 2OUT through a feedback network and AC-coupled from 1OUT via C4.
14	1IN+	input	First-stage op-amp (OP1) non-inverting input. Typically driven from the pyroelectric PIR sensor output.
15	1IN-	input	First-stage op-amp (OP1) inverting input. Used with an external RC feedback network to set OP1 gain.
16	1OUT	output	First-stage op-amp (OP1) output. AC-coupled to OP2 via C4 for second-stage amplification.

Key specifications

Parameter	Value
Manufacturer	HANSCHIP semiconductor
Package	SOP-16
Category	Sensor
Pins	16

Ordering variants

BISS0001DRG
BISS0001DRGPG
BISS0001DRGPWRG

CAD (KiCad official)

Symbol: BISS0001DRG
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOP-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: HANSCHIP semiconductor datasheet (10 pp, sha256 a73355c54bc97db2, retrieved 2026-08-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF