BISS0001 from GR, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	A	input	Retrigger mode select. A=1 enables retriggerable mode (Vo can be re-extended by new Vs edges); A=0 selects non-retriggerable mode (Vs edges ignored during Tx). VAH >= 3.5 V, VAL <= 1.5 V at VDD=5 V.
2	VO	output	Control signal output. Driven high by a rising edge of the internal Vs comparator output; remains high for the output-delay time Tx, then returns low. VOH >= 4 V, VOL <= 0.4 V at VDD=5 V.
3	RR1	passive	Output-delay-time (Tx) adjustment. External resistor R1 to VDD together with capacitor C1 on RC1 sets Tx ~= 67025 * R1 * C1.
4	RC1	passive	Output-delay-time (Tx) adjustment. External capacitor C1 to VSS together with resistor R1 on RR1 sets Tx ~= 67025 * R1 * C1.
5	RC2	passive	Inhibit (blocking) time (Ti) adjustment. External capacitor C2 to VSS together with resistor R2 on RR2 sets Ti ~= 60 * R2 * C2.
6	RR2	passive	Inhibit (blocking) time (Ti) adjustment. External resistor R2 together with capacitor C2 on RC2 sets Ti ~= 60 * R2 * C2.
7	VSS	power_in	Negative supply / ground. Normally tied to 0 V.
8	VRF/RESET	input	Reference-voltage and reset input. Normally tied to VDD for normal operation; pulling to 0 resets the internal timers.
9	VC	input	Trigger-inhibit input. Compared against internal VR ~= 0.2*VDD: when VC<VR triggering is blocked; when VC>VR triggering is enabled. Typically driven from an ambient-light (CdS) sensor. VRH >= 1.1 V, VRL <= 0.9 V at VDD=5 V.
10	IB	passive	Op-amp bias-current setting. External resistor RB (~1 M-ohm) to VSS sets the internal op-amp bias current.
11	VDD	power_in	Positive supply, 3.0-5.0 V operating range (absolute max +6 V). Typical IDD 50 uA at 3 V (loaded) / 100 uA at 5 V (no load).
12	2OUT	output	Second-stage op-amp (OP2) output. Feeds the internal bidirectional window comparator (COP1/COP2, VH ~= 0.7VDD, VL ~= 0.3VDD).
13	2IN-	input	Second-stage op-amp (OP2) inverting input. Non-inverting input is internally biased to VM ~= 0.5*VDD.
14	1IN+	input	First-stage op-amp (OP1) non-inverting input. High-input-impedance CMOS input for direct connection to PIR sensor.
15	1IN-	input	First-stage op-amp (OP1) inverting input.
16	1OUT	output	First-stage op-amp (OP1) output. Open-loop gain Avo >= 60 dB; output swing VYH >= 4.25 V, VYL <= 0.75 V at VDD=5 V.

Key specifications

Parameter	Value
Manufacturer	GR
Package	SOP-16
Category	Sensor
Pins	16

CAD (KiCad official)

Symbol: BISS0001
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOP-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`biss0001.step`	217 KB	You want the bare part, or you mark your own boards.
`biss0001-etched.step`	2.6 MB	You want the part with `BISS0001` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 625 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: GR datasheet (6 pp, sha256 2062bc65634236c9, retrieved 2026-08-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF