component
BDR6300
Public Unreviewedby Ray
Bardeen Micro Brushless DC (BLDC) Motor Driver, SOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Symbol & Footprint
Schematic Symbol
Open full view ↗PCB Footprint
Open full view ↗Datasheet
Open in new tab ↗README
markdownBDR6300
Bardeen Micro · Brushless DC (BLDC) Motor Driver · SOP-16
BDR6300 from Bardeen Micro, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Main power supply input, also feeds the internal LDO. Operating range 12V to 30V. May be externally tied to VCC. |
| 2 | VCC | power_in | PMOS driver stage supply. Recommended operating range 8V to 30V (typ 24V). May be externally tied to VDD. |
| 3 | P3_OUT | output | Phase-3 PMOS gate drive output. Inverted with respect to P3_IN (high when P3_IN floats or is low, low when P3_IN is high). Drives directly to PMOS gate. |
| 4 | N3_OUT | output | Phase-3 NMOS gate drive output. Follows N3_IN (low when floating or low, high when high). |
| 5 | P2_OUT | output | Phase-2 PMOS gate drive output. Inverted with respect to P2_IN. Drives PMOS gate directly. |
| 6 | N2_OUT | output | Phase-2 NMOS gate drive output. Follows N2_IN. |
| 7 | P1_OUT | output | Phase-1 PMOS gate drive output. Inverted with respect to P1_IN. Drives PMOS gate directly. |
| 8 | N1_OUT | output | Phase-1 NMOS gate drive output. Follows N1_IN. |
| 9 | N1_IN | input | Phase-1 NMOS logic input. Internal 16k pull-down to GND - floats low. Drive high to turn on NMOS. |
| 10 | P1_IN | input | Phase-1 PMOS logic input. Internal 8k pull-up to VCC - floats high (PMOS off). Drive low to turn on PMOS. |
| 11 | N2_IN | input | Phase-2 NMOS logic input. Internal 16k pull-down. Drive high to enable NMOS gate output. |
| 12 | P2_IN | input | Phase-2 PMOS logic input. Internal 8k pull-up. Input current ~1.1mA at 5V drive. Drive low to enable PMOS gate output. |
| 13 | N3_IN | input | Phase-3 NMOS logic input. Internal 16k pull-down. Drive high to enable NMOS gate output. |
| 14 | P3_IN | input | Phase-3 PMOS logic input. Internal 8k pull-up. Drive low to enable PMOS gate output. |
| 15 | GND | power_in | Ground reference for the IC. |
| 16 | +5V | power_out | LDO regulated output, 4.8V/5.0V/5.3V (min/typ/max). Supplies up to 60mA when VDD<24V. Bypass with a ceramic capacitor to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Bardeen Micro |
| Package | SOP-16 |
| Category | Motor Driver ICs |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
BDR6300 - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOP-16 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Bardeen Micro datasheet (6 pp, sha256
97f9c9c9d046c8b0, retrieved 2026-08-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).