BD9B400MUV-E2 from ROHM, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PVIN	power_in	Power supply input to the switching regulator output stage (2.7 V to 5.5 V). Tied in parallel with pin 2. Requires a 22µF ceramic bypass capacitor.
2	PVIN	power_in	Power supply input to the switching regulator output stage (2.7 V to 5.5 V). Tied in parallel with pin 1.
3	PGND	power_in	Power ground for the switching regulator output stage. Tied in parallel with pin 4.
4	PGND	power_in	Power ground for the switching regulator output stage. Tied in parallel with pin 3.
5	AGND	power_in	Analog ground for the control circuit. Kelvin-connect to PGND at a single point.
6	FB	input	Feedback input, the inverting input to the error amplifier and main comparator. Regulates to VFB = 0.8 V (typ, 0.792-0.808 V) via an external resistor divider from VOUT.
7	FREQ	input	Switching-frequency select. Tie to GND for constant on-time corresponding to 2 MHz; tie to AVIN for 1 MHz. Must be fixed to AVIN or ground in operation.
8	MODE	input	Switching-control mode select. Tie to AVIN for fixed-frequency PWM; tie to GND to enable Deep-SLLM auto mode (auto switching between Deep-SLLM and fixed PWM). Must be fixed to AVIN or ground in operation.
9	SS	passive	Soft-start timing. Connect a capacitor to GND to set the output-voltage rise time; internal soft-start current ISS ≈ 1 µA (typ). Internal soft-start defaults to 1 ms (typ) when SS is open.
10	SW	power_out	Switch node - source of the high-side MOSFET and drain of the low-side MOSFET. Pins 10, 11, 12 are internally connected; connect the output inductor here (0.47µH-1µH for FREQ=L, 1µH-1.5µH for FREQ=H).
11	SW	power_out	Switch node (paralleled with pins 10 and 12).
12	SW	power_out	Switch node (paralleled with pins 10 and 11). A 0.1µF bootstrap capacitor between SW and BOOT is required.
13	BOOT	passive	Bootstrap capacitor node for the high-side MOSFET gate drive. Connect a 0.1µF ceramic capacitor between BOOT and SW; V(BOOT-SW) is the high-side gate-drive supply (~5 V).
14	PGD	output	Power-Good open-drain output. Requires an external pull-up resistor. Goes high-Z (High) when VFB exceeds 80% of 0.8 V; RPGD ≈ 100 Ω (typ), max sink 1 mA gives VOL ≈ 0.1 V.
15	EN	input	Enable input. Drive Low (≤0.8 V) to enter shutdown; drive High (≥2.0 V) to enable the device. IEN ≈ 5 µA @ EN=5V. Must be terminated (no internal pull).
16	AVIN	power_in	Analog/control-circuit supply (2.7 V to 5.5 V). Must be connected to PVIN. A 0.1µF ceramic bypass capacitor is recommended.
17	E-Pad	power_in	Backside exposed thermal pad. Connect to the internal PCB ground plane with multiple thermal vias for heat dissipation.

Key specifications

Parameter	Value
Manufacturer	ROHM
Package	VQFN-16-EP(3x3)
Category	PMIC
Pins	17

Ordering variants

Same part, different packaging or reel option.

BD9B400MUV-E2

CAD (KiCad official)

Symbol: BD9B400MUV-E2
Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: ROHM datasheet (33 pp, sha256 775e756d99121154, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF