ATTINY43U-MU from Microchip Tech, in a QFN-20-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PB2	bidirectional	Port B bit 2. General-purpose I/O with internal pull-up. Alternate functions: OC0B (Timer/Counter0 compare match B output / PWM) and PCINT10 (pin-change interrupt). Tri-stated during reset. Vih ≥ 0.6·VCC, Vil ≤ 0.3·VCC; ~40 mA sink/source per pin (symmetrical drive).
2	PB3	bidirectional	Port B bit 3. General-purpose I/O with internal pull-up. Alternate functions: T1 (Timer/Counter1 external clock input), CLKO (system clock output when CKOUT fuse is programmed) and PCINT11.
3	PB4	bidirectional	Port B bit 4. General-purpose I/O with internal pull-up. Alternate functions: DI (USI three-wire data-input / SPI MOSI), OC1A (Timer/Counter1 PWM output A) and PCINT12.
4	PB5	bidirectional	Port B bit 5. General-purpose I/O with internal pull-up. Alternate functions: DO (USI three-wire data-output / SPI MISO), OC1B (Timer/Counter1 PWM output B) and PCINT13.
5	PB6	bidirectional	Port B bit 6. General-purpose I/O with internal pull-up. Alternate functions: USCK (USI clock line for three-wire/SPI mode), SCL (USI clock line for two-wire/I²C mode) and PCINT14.
6	PB7	bidirectional	Port B bit 7. General-purpose I/O with internal pull-up. Alternate functions: INT0 (external interrupt request 0 input) and PCINT15.
7	VCC	power_in	Digital supply voltage. 1.8 - 5.5 V when the on-chip boost converter is bypassed. When the boost converter is used, VCC is driven internally from VBAT (0.7 - 1.8 V) via the LSW inductor node; VCC is then the boosted rail. Decouple close to the pin.
8	GND	power_in	Ground reference for the whole device. Tie the QFN exposed pad to the same GND net.
9	LSW	passive	Boost-converter switching node - connects to the external boost inductor (the other end goes to VBAT). Internally the low-side switch of the boost converter pulls this node to GND at the switching frequency. Tie directly to GND if the boost converter will be permanently disabled.
10	VBAT	power_in	Battery / low-voltage input to the on-chip boost converter (0.7 - 1.8 V nominal). Also the far end of the boost inductor. Tie to GND if the boost converter will be permanently disabled.
11	PA0	bidirectional	Port A bit 0. General-purpose I/O with internal pull-up. Alternate functions: ADC0 (10-bit ADC single-ended channel 0) and PCINT0.
12	PA1	bidirectional	Port A bit 1. General-purpose I/O with internal pull-up. Alternate functions: ADC1 (10-bit ADC channel 1) and PCINT1.
13	PA2	bidirectional	Port A bit 2. General-purpose I/O with internal pull-up. Alternate functions: ADC2 (10-bit ADC channel 2) and PCINT2.
14	PA3	bidirectional	Port A bit 3. General-purpose I/O with internal pull-up. Alternate functions: ADC3 (10-bit ADC channel 3) and PCINT3.
15	PA4	bidirectional	Port A bit 4. General-purpose I/O with internal pull-up. Alternate functions: AIN0 (positive input of the on-chip analog comparator) and PCINT4.
16	PA5	bidirectional	Port A bit 5. General-purpose I/O with internal pull-up. Alternate functions: AIN1 (negative input of the on-chip analog comparator) and PCINT5.
17	PA6	bidirectional	Port A bit 6. General-purpose I/O with internal pull-up. Alternate functions: CLKI (external clock input when the External Clock system-clock source is selected by fuses) and PCINT6.
18	PA7	bidirectional	Port A bit 7 / RESET. When the RSTDISBL fuse is unprogrammed this pin is the active-low external RESET input (a low pulse longer than the minimum pulse length triggers a reset even without a running clock). Programming RSTDISBL (=0) turns the pin into a normal GPIO - but then further ISP is only possible via High-Voltage Serial Programming. Also carries the debugWIRE (dW) signal for on-chip debug/programming and PCINT7.
19	PB0	bidirectional	Port B bit 0. General-purpose I/O with internal pull-up. Alternate functions: T0 (Timer/Counter0 external clock input) and PCINT8.
20	PB1	bidirectional	Port B bit 1. General-purpose I/O with internal pull-up. Alternate functions: OC0A (Timer/Counter0 compare match A output / PWM) and PCINT9.
EP	EP	power_in	Exposed thermal / centre pad on the underside of the QFN/MLF package. Per the datasheet note, must be soldered to ground (tie to GND net).

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	QFN-20-EP(4x4)
Category	Embedded Processors & Controllers
Pins	21

Ordering variants

Same part, different packaging or reel option.

ATTINY43U-MU
ATTINY43U-MUR
ATTINY43U-MUSU
ATTINY43U-MUSUR

CAD (KiCad official)

Symbol: ATTINY43U-MU
Footprint: Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
3D model: QFN-20-EP(4x4) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (210 pp, sha256 5e4f91d02c1ae2a1, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF