ATMEGA1608-MU from Microchip Tech, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PA3	bidirectional	PORT A bit 3. GPIO on VDD domain. Alt functions: TWI0 (SCL master-slave alt), USART0 XDIR, TCA0 WO3, TCB1 WO, CCL LUT0-OUT.
2	PA4	bidirectional	PORT A bit 4. GPIO on VDD domain. Alt functions: USART0 TxD (alt), SPI0 MOSI, TCA0 WO4.
3	PA5	bidirectional	PORT A bit 5. GPIO on VDD domain. Alt functions: USART0 RxD (alt), SPI0 MISO, TCA0 WO5.
4	PA6	bidirectional	PORT A bit 6. GPIO on VDD domain. Alt functions: USART0 XCK (alt), SPI0 SCK, AC0 OUT (alt).
5	PA7	bidirectional	PORT A bit 7. GPIO on VDD domain. Alt functions: CLKOUT, AC0 OUT, USART0 XDIR (alt), SPI0 SS, EVOUTA (alt).
6	PC0	bidirectional	PORT C bit 0. GPIO on VDD domain. Alt functions: USART1 TxD, SPI0 MOSI (alt), TCA0 WO0 (alt), TCB2 WO, CCL LUT1-IN0.
7	PC1	bidirectional	PORT C bit 1. GPIO on VDD domain. Alt functions: USART1 RxD, SPI0 MISO (alt), TCA0 WO1 (alt), CCL LUT1-IN1.
8	PC2	bidirectional	PORT C bit 2. GPIO on VDD domain. Alt functions: TWI0 (SCK/SDA master-slave alt), USART1 XCK, SPI0 SCK (alt), TCA0 WO2 (alt), EVOUTC, CCL LUT1-IN2.
9	PC3	bidirectional	PORT C bit 3. GPIO on VDD domain. Alt functions: TWI0 (SCL master-slave alt), USART1 XDIR, SPI0 SS (alt), TCA0 WO3 (alt), CCL LUT1-OUT.
10	PD0	bidirectional	PORT D bit 0. GPIO on AVDD (analog) domain. Alt functions: ADC0 AIN0, TCA0 WO0 (alt), CCL LUT2-IN0.
11	PD1	bidirectional	PORT D bit 1. GPIO on AVDD (analog) domain. Alt functions: ADC0 AIN1, AC0 P3, TCA0 WO1 (alt), CCL LUT2-IN1.
12	PD2	bidirectional	PORT D bit 2. GPIO on AVDD (analog) domain. Alt functions: ADC0 AIN2, AC0 P0, TCA0 WO2 (alt), EVOUTD, CCL LUT2-IN2.
13	PD3	bidirectional	PORT D bit 3. GPIO on AVDD (analog) domain. Alt functions: ADC0 AIN3, AC0 N0, TCA0 WO3 (alt), CCL LUT2-OUT.
14	PD4	bidirectional	PORT D bit 4. GPIO on AVDD (analog) domain. Alt functions: ADC0 AIN4, AC0 P1, TCA0 WO4 (alt).
15	PD5	bidirectional	PORT D bit 5. GPIO on AVDD (analog) domain. Alt functions: ADC0 AIN5, AC0 N1, TCA0 WO5 (alt).
16	PD6	bidirectional	PORT D bit 6. GPIO on AVDD (analog) domain. Alt functions: ADC0 AIN6, TCB2 WO (alt).
17	PD7	bidirectional	PORT D bit 7. GPIO on AVDD (analog) domain. Alt functions: VREFA external voltage reference input, ADC0 AIN7, AC0 N2, EVOUTD (alt).
18	AVDD	power_in	Analog supply voltage (1.8-5.5 V). Must be tied to the same rail as VDD; supplies the ADC, AC and PORT-D/F analog domain. Decouple with a 100 nF ceramic close to the pin.
19	GND	power_in	Ground reference for the analog and digital supply. All GND pins must be connected to the board's ground plane.
20	PF0/TOSC1	bidirectional	PORT F bit 0 / TOSC1 32.768 kHz crystal input for the RTC. Alt functions: USART2 TxD, TCA0 WO0 (alt), CCL LUT3-IN0.
21	PF1/TOSC2	bidirectional	PORT F bit 1 / TOSC2 32.768 kHz crystal output for the RTC. Alt functions: USART2 RxD, TCA0 WO1 (alt), CCL LUT3-IN1.
22	PF2	bidirectional	PORT F bit 2. Alt functions: TWI0 SDA (slave alt), ADC0 AIN12, USART2 XCK, TCA0 WO2 (alt), EVOUTF, CCL LUT3-IN2.
23	PF3	bidirectional	PORT F bit 3. Alt functions: TWI0 SCL (slave alt), ADC0 AIN13, USART2 XDIR, TCA0 WO3 (alt), CCL LUT3-OUT.
24	PF4	bidirectional	PORT F bit 4. Alt functions: ADC0 AIN14, USART2 TxD (alt), TCA0 WO4 (alt), TCB0 WO (alt).
25	PF5	bidirectional	PORT F bit 5. Alt functions: ADC0 AIN15, USART2 RxD (alt), TCA0 WO5 (alt), TCB1 WO (alt).
26	PF6/RESET	bidirectional	PORT F bit 6 / external RESET input (active-low). Function selected by the RSTPINCFG fuse: default is GPIO input; when configured as RESET, drive low to reset the device (internal pull-up present). Alt functions: USART2 XCK (alt), CCL LUT3-OUT (alt).
27	UPDI	bidirectional	Unified Program and Debug Interface. Single-wire bidirectional pin used by the UPDI programmer/debugger; keep accessible on a programming header (e.g. 4.7 kΩ series to protect against contention).
28	VDD	power_in	Digital supply voltage (1.8-5.5 V). Decouple with a 100 nF ceramic close to the pin; supplies the CPU core, PORT A/C/F digital domain and peripherals.
29	GND	power_in	Ground reference for the digital supply. Tie to the board's ground plane together with pin 19.
30	PA0/EXTCLK	bidirectional	PORT A bit 0 / external clock input (EXTCLK). Alt functions: USART0 TxD, TCA0 WO0, CCL LUT0-IN0.
31	PA1	bidirectional	PORT A bit 1. GPIO on VDD domain. Alt functions: USART0 RxD, TCA0 WO1, CCL LUT0-IN1.
32	PA2	bidirectional	PORT A bit 2. GPIO on VDD domain. Alt functions: TWI0 SDA (master-slave default), USART0 XCK, TCA0 WO2, TCB0 WO, EVOUTA, CCL LUT0-IN2.
EP	EP	passive	Exposed thermal pad on the underside of the VQFN package. Datasheet states it may be left electrically unconnected but must be soldered or glued for mechanical stability; commonly tied to GND for best thermal/EMI performance.

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	VQFN-32-EP(5x5)
Category	Embedded Processors & Controllers
Pins	33

Ordering variants

Same part, different packaging or reel option.

ATMEGA1608-MU
ATMEGA1608-MUR
ATMEGA1608-MUMF
ATMEGA1608-MUMFR
ATMEGA1608-MUAU
ATMEGA1608-MUAUR
ATMEGA1608-MUAF
ATMEGA1608-MUAFR
ATMEGA1608-MUXU
ATMEGA1608-MUXUR
ATMEGA1608-MUXF
ATMEGA1608-MUXFR

CAD (KiCad official)

Symbol: ATMEGA1608-MU
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (None pp, sha256 11b98b7b422fa15b, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF