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README

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ATM2310NSA

Agertech · MOSFETs · SOT-23

ATM2310NSA from Agertech, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate. Insulated MOSFET control terminal; VGS(th) ≈ 1-2.5 V, VGS absolute maximum ±20 V. Drive VGS ≥ 4.5 V for logic-level switching (RDS(on) ≤ 110 mΩ) or VGS = 10 V for full enhancement (RDS(on) ≤ 100 mΩ).
2 S passive Source. Common terminal for the channel and the intrinsic body diode anode. Typically tied to the low-side / battery-negative reference in a switching application.
3 D passive Drain. Switched high-side terminal; VDS absolute maximum 60 V, ID = 3 A continuous, 10 A pulsed. Also the intrinsic body-diode cathode (VSD ≈ 1.2 V at IS = 1 A).

Key specifications

Parameter Value
Manufacturer Agertech
Package SOT-23
Category Transistors/Thyristors
Pins 3

CAD (KiCad official)

  • Symbol: ATM2310NSA
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Agertech datasheet (None pp, sha256 f0b552931c26d6e8, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF