AP7362-33SP-13 from Diodes Incorporated, in a SO-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GND	power_in	Device ground return. Also serves as the reference for the internal band-gap and output feedback network. Should be tied to the exposed pad copper plane.
2	EN	input	Enable input, active high. VIH ≥ 1.4V turns the regulator on; VIL ≤ 0.65V places the device in shutdown (IGND ≈ 25nA). Absolute-max range -0.3V to 6.0V; do not float.
3	IN	power_in	Voltage input pin. Operating range 2.2V to 5.5V (absolute-max 6.0V). Pins 3 and 4 are internally connected and must be tied together on the PCB; place a ≥10µF input capacitor close to these pins.
4	IN	power_in	Voltage input pin. Internally strapped to pin 3; tie both externally and decouple with a ≥10µF ceramic input capacitor.
5	OUT	power_out	Regulated 3.3V output pin (fixed AP7362-33 variant). Rated 1.5A continuous. Pins 5, 6, 7 are internally connected and must be tied together; requires a ≥10µF output capacitor (any type) for stability.
6	OUT	power_out	Regulated output pin, internally strapped to pins 5 and 7. Tie all three externally to share the 1.5A load current and reduce metal resistance.
7	OUT	power_out	Regulated output pin, internally strapped to pins 5 and 6. Tie all three externally at the ≥10µF output capacitor.
8	NC	unconnected	No internal connection on this fixed-output (AP7362-33) variant. On the adjustable AP7362 variant this pin is the ADJ feedback input; leave it open or tie to ground for the fixed version.
EP	EP	power_in	Exposed thermal pad on the package underside. Die is electrically connected to EP; must be soldered to a copper area for heat removal (θJA ≈ 52.8 °C/W). Connect externally to GND, but do not use as the only ground connection.

Key specifications

Parameter	Value
Manufacturer	Diodes Incorporated
Package	SO-8-EP
Category	PMIC
Pins	9

Ordering variants

AP7362-33SP-13
AP7362-33SP-13HA-7

CAD (KiCad official)

Symbol: AP7362-33SP-13
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SO-8-EP (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`ap7362-33sp-13.step`	122 KB	You want the bare part, or you mark your own boards.
`ap7362-33sp-13-etched.step`	2.9 MB	You want the part with `AP7362-33SP-13` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 695 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Diodes Incorporated datasheet (15 pp, sha256 9b2fca67bed660a2, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF