ADS8671IPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	DGND	power_in	Digital ground pin. Decouple with the DVDD pin. Connect to system digital ground plane.
2	AVDD	power_in	Analog supply pin, 4.75 V to 5.25 V (nominal 5 V). Decouple with the AGND pin.
3	AGND	power_in	Analog ground pin. Decouple with the AVDD pin. Connect to system analog ground plane.
4	REFIO	bidirectional	Internal 4.096-V reference output and external reference input pin. Decouple with REFGND.
5	REFGND	power_in	Reference ground pin; short to the analog ground plane. Decouple with the REFIO and REFCAP pins.
6	REFCAP	passive	ADC reference buffer decoupling capacitor pin. Decouple with the REFGND pin (typically a low-ESR ceramic capacitor as recommended in the datasheet).
7	AIN_P	input	Positive analog input to the ADC. Full-scale input span (AIN_P to AIN_GND) is software-selectable between ±12.288 V, ±10.24 V, ±6.144 V, ±5.12 V, ±2.56 V (bipolar) or 0-12.288 V, 0-10.24 V, 0-6.144 V, 0-5.12 V (unipolar). Constant input impedance ≥ 1 MΩ. Overvoltage protection up to ±20 V with AVDD = 5 V.
8	AIN_GND	input	Negative analog input (ADC reference-side input). Operating input range -0.1 V to 0.1 V (typ 0 V). Decouple with the AIN_P pin.
9	RST	input	Active-low asynchronous reset input. Referenced to DVDD I/O rail (1.65 V-5.25 V).
10	SDI	input	Serial data input pin for SPI-compatible interface. Also acts as chain data input during daisy-chain mode.
11	CONVST/CS	input	Dual-function pin. In active-high (CONVST) mode a rising edge starts a conversion, moving the device from acquisition to conversion phase. In active-low (CS) mode this is a chip-select input; the device takes control of the data bus while CS is low, and SDO-x pins go tri-state when CS is high.
12	SCLK	input	Serial interface clock input. All system-synchronous data-transfer protocols are timed with respect to SCLK.
13	SDO-0	tri_state	Primary serial data output pin (data output 0). Goes tri-state when CS is deasserted (high).
14	ALARM/SDO-1/GPO	tri_state	Multi-function digital output. Configurable as an active-high ALARM output (input overrange/threshold), a second serial data output (SDO-1) for the multiSPI dual-SDO protocol, or a general-purpose output (GPO).
15	RVS	output	Multi-function output for the serial interface. With CS held high, RVS reflects the internal ADCST (ADC status) signal. With CS low, the RVS behavior depends on the selected output protocol (data-valid/data-ready strobe).
16	DVDD	power_in	Digital I/O supply, 1.65 V to AVDD (nominal 3.3 V). Sets logic levels for all digital pins. Decouple with the DGND pin.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-16
Category	Data Acquisition
Pins	16

Ordering variants

Same part, different packaging or reel option.

ADS8671IPWR

CAD (KiCad official)

Symbol: ADS8671IPWR
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (None pp, sha256 821d4c36b8c60300, retrieved 2026-08-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF