Symbol & Footprint

Schematic Symbol

Open full view ↗

PCB Footprint

Open full view ↗
Contents

README

markdown

ADS131E08IPAGR

Texas Instruments · Analog Front End (AFE) · TQFP-64(10x10)

ADS131E08IPAGR from Texas Instruments, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN8N input Negative analog input for channel 8. Connect unused input pins to AVDD via a resistor.
2 IN8P input Positive analog input for channel 8. Connect unused input pins to AVDD via a resistor.
3 IN7N input Negative analog input for channel 7. Connect unused input pins to AVDD via a resistor.
4 IN7P input Positive analog input for channel 7. Connect unused input pins to AVDD via a resistor.
5 IN6N input Negative analog input for channel 6. Connect unused input pins to AVDD via a resistor.
6 IN6P input Positive analog input for channel 6. Connect unused input pins to AVDD via a resistor.
7 IN5N input Negative analog input for channel 5. Connect unused input pins to AVDD via a resistor.
8 IN5P input Positive analog input for channel 5. Connect unused input pins to AVDD via a resistor.
9 IN4N input Negative analog input for channel 4. Connect unused input pins to AVDD via a resistor.
10 IN4P input Positive analog input for channel 4. Connect unused input pins to AVDD via a resistor.
11 IN3N input Negative analog input for channel 3. Connect unused input pins to AVDD via a resistor.
12 IN3P input Positive analog input for channel 3. Connect unused input pins to AVDD via a resistor.
13 IN2N input Negative analog input for channel 2. Connect unused input pins to AVDD via a resistor.
14 IN2P input Positive analog input for channel 2. Connect unused input pins to AVDD via a resistor.
15 IN1N input Negative analog input for channel 1. Connect unused input pins to AVDD via a resistor.
16 IN1P input Positive analog input for channel 1. Connect unused input pins to AVDD via a resistor.
17 TESTP bidirectional Test signal, positive pin. See the Unused Inputs and Outputs section for unused pin handling.
18 TESTN bidirectional Test signal, negative pin. See the Unused Inputs and Outputs section for unused pin handling.
19 AVDD power_in Analog supply (3 V to 5 V unipolar, or ±2.5 V bipolar). Connect a 1-µF (or larger) capacitor to AVSS for each AVDD pin.
20 AVSS power_in Analog ground.
21 AVDD power_in Analog supply. Connect a 1-µF (or larger) capacitor to AVSS for each AVDD pin.
22 AVDD power_in Analog supply. Connect a 1-µF (or larger) capacitor to AVSS for each AVDD pin.
23 AVSS power_in Analog ground.
24 VREFP bidirectional Positive reference voltage. Connect a minimum 10-µF capacitor to VREFN.
25 VREFN input Negative reference voltage. Connect to AVSS.
26 VCAP4 output Analog bypass capacitor. Connect a 1-µF capacitor to AVSS.
27 NC unconnected No connection; leave floating. May be tied to AVDD or AVSS through a 10-kΩ or higher resistor.
28 VCAP1 output Analog bypass capacitor. Connect a 22-µF capacitor to AVSS.
29 NC unconnected No connection; leave floating. May be tied to AVDD or AVSS through a 10-kΩ or higher resistor.
30 VCAP2 output Analog bypass capacitor. Connect a 1-µF capacitor to AVSS.
31 RESV1 input Reserved for future use. Connect directly to DGND.
32 AVSS power_in Analog ground.
33 DGND power_in Digital ground.
34 DIN input Serial data input (SPI MOSI).
35 PWDN input Power-down; active low.
36 RESET input System reset; active low.
37 CLK input Master clock input. Connect to DGND if unused (internal oscillator selected via CLKSEL).
38 START input Start conversion. A rising edge (or held high) starts ADC conversions.
39 CS input Chip select; active low. Enables the SPI interface.
40 SCLK input Serial clock input (SPI SCLK).
41 DAISY_IN input Daisy-chain data input for cascading multiple devices on the SPI bus. Connect to DGND if unused.
42 GPIO1 bidirectional General-purpose input/output pin 1. Connect to DGND via a 10-kΩ resistor if unused.
43 DOUT output Serial data output (SPI MISO).
44 GPIO2 bidirectional General-purpose input/output pin 2. Connect to DGND via a 10-kΩ resistor if unused.
45 GPIO3 bidirectional General-purpose input/output pin 3. Connect to DGND via a 10-kΩ resistor if unused.
46 GPIO4 bidirectional General-purpose input/output pin 4. Connect to DGND via a 10-kΩ resistor if unused.
47 DRDY output Data ready; active low. Indicates new conversion data is available. Connect to DGND with a 10-kΩ resistor if unused.
48 DVDD power_in Digital core power supply (1.8 V to 3.6 V). Connect a 1-µF (or larger) capacitor to DGND for each DVDD pin.
49 DGND power_in Digital ground.
50 DVDD power_in Digital core power supply. Connect a 1-µF (or larger) capacitor to DGND for each DVDD pin.
51 DGND power_in Digital ground.
52 CLKSEL input Master clock select: chooses between the external CLK input and the internal oscillator.
53 AVSS1 power_in Charge-pump analog ground.
54 AVDD1 power_in Charge-pump analog supply. Connect a 1-µF (or larger) capacitor to AVSS1.
55 VCAP3 output Analog bypass capacitor. Connect a parallel combination of 1-µF and 0.1-µF capacitors to AVSS.
56 AVDD power_in Analog supply. Connect a 1-µF (or larger) capacitor to AVSS for each AVDD pin.
57 AVSS power_in Analog ground.
58 AVSS power_in Analog ground.
59 AVDD power_in Analog supply. Connect a 1-µF (or larger) capacitor to AVSS for each AVDD pin.
60 OPAMPP input Op-amp noninverting input; leave floating and power the op amp down if unused.
61 OPAMPN input Op-amp inverting input; leave floating and power the op amp down if unused.
62 NC unconnected No connection; leave floating. May be tied to AVDD or AVSS through a 10-kΩ or higher resistor.
63 OPAMPOUT output Op-amp output; leave floating and power the op amp down if unused.
64 NC unconnected No connection; leave floating. May be tied to AVDD or AVSS through a 10-kΩ or higher resistor.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-64(10x10)
Category Data Acquisition
Pins 64

Ordering variants

Same part, different packaging or reel option.

  • ADS131E08IPAGR

CAD (KiCad official)

  • Symbol: ADS131E08IPAGR
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (75 pp, sha256 be5dbbec27fb28d4, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF