component

ADP1051ACPZ-R7

Public Unreviewed

by Ray

Analog Devices Supervisor And Reset ICs, LFCSP-24(4x4). Datasheet-verified pinout, KiCad symbol/footprint/3D.

componentpower management (pmic)adp1051acpz-r7
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads on click. Unloads when scrolled away or the tab is hidden.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads when scrolled away or the tab is hidden.

PCB Footprint

Open full view ↗
Loads on click. Unloads when scrolled away or the tab is hidden.

Datasheet

Open in new tab ↗
Loads on click. Unloads when scrolled away or the tab is hidden.
Download PDF
Contents

README

markdown

ADP1051ACPZ-R7

Analog Devices · Supervisor And Reset ICs · LFCSP-24(4x4)

ADP1051ACPZ-R7 from Analog Devices, in a LFCSP-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VS- input Inverting Voltage Sense Input. Connection for the ground line of the output power rail; must have a low-ohmic connection to AGND. External resistor divider tolerance <=0.5% is recommended to allow for trimming.
2 VS+ input Noninverting Voltage Sense Input, referred to VS-. External resistor divider tolerance <=0.5% is recommended to allow for trimming.
3 CS2- input Inverting Differential Current Sense Input. Nominal 1.12 V. Use a 4.99 kOhm level-shift resistor for low-side sensing or 5.62 kOhm for high-side sensing in a 12 V application (0.1% tolerance). Tie to AGND if unused and configure Register 0xFE19[7]=1 for high-side sense mode.
4 CS2+ input Noninverting Differential Current Sense Input. Nominal 1.12 V. Same level-shifting and configuration rules as CS2-; tie to AGND if unused.
5 VF input Voltage Feedforward / Primary-Side Input Voltage Sense / Input UVLO Protection. Connected upstream of the output inductor through a resistor divider; nominal voltage 1 V, referred to AGND.
6 CS1 input Primary Side Current Sense Input feeding the primary-side current-sensing ADC and cycle-by-cycle current-limit comparator. Resistors on this input must be <=0.5% tolerance for trimming. Tie to AGND if unused.
7 SR1 output PWM Logic Output Drive (synchronous rectifier). Referred to AGND; can be disabled when not in use.
8 SR2 output PWM Logic Output Drive (synchronous rectifier). Referred to AGND; can be disabled when not in use.
9 OUTA output PWM Logic Output Drive. Referred to AGND; can be disabled when not in use.
10 OUTB output PWM Logic Output Drive. Referred to AGND; can be disabled when not in use.
11 OUTC output PWM Logic Output Drive. Referred to AGND; can be disabled when not in use. Can also be programmed as a synchronization signal output (SYNO).
12 OUTD output PWM Logic Output Drive. Referred to AGND; can be disabled when not in use. Can also be programmed as a synchronization signal output (SYNO).
13 SYNI/FLGI input Synchronization Signal Input (SYNI) or External Signal Input to generate a flag condition (FLGI). Tie to AGND if unused.
14 SCL bidirectional I2C/PMBus Serial Clock Input and Output (open drain), referred to AGND. Requires an external pull-up resistor.
15 SDA bidirectional I2C/PMBus Serial Data Input and Output (open drain), referred to AGND. Requires an external pull-up resistor.
16 CTRL input PMBus Control Signal input. Referred to AGND; a 1 nF decoupling capacitor to AGND is recommended for noise debounce.
17 PG/ALT output Power Good Output / SMBus ALERT (open drain). Connect to VDD via a pull-up (typically 2.2 kOhm); referred to AGND.
18 VCORE power_out Output of internal 2.6 V regulator. Decouple with at least 330 nF to AGND placed close to the device. Not intended to source current for external loads or to be used as a reference.
19 VDD power_in Positive Supply Input, 3.0 V to 3.6 V, referred to AGND. Decouple with a 2.2 uF capacitor to AGND placed close to the device.
20 AGND power_in Common Analog Ground. Internal analog and digital circuitry grounds are star-connected to this pin through bonding wires.
21 RES passive Resistor Input that sets the internal reference for the internal PLL frequency. Connect a 10 kOhm (+/-0.1%) resistor from RES to AGND.
22 ADD input Address Select Input for the I2C/PMBus address. Connect an external resistor from ADD to AGND to program the device address.
23 RTD input Thermistor Input. Place a thermistor (R25 = 100 kOhm 1%, beta = 4250 1%) in parallel with a 16.5 kOhm (1%) resistor and a 1 nF filter capacitor. Referred to AGND; tie to AGND if unused.
24 OVP input Overvoltage Protection input used as redundant overvoltage protection. Referred to AGND.
EP EP power_in Exposed Thermal Pad on the underside of the package. For solder-joint reliability and maximum thermal capability, solder to the PCB AGND plane.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-24(4x4)
Category Power Management (PMIC)
Pins 25

Ordering variants

Same part, different packaging or reel option.

  • ADP1051ACPZ-R7
  • ADP1051ACPZ-RL

CAD (KiCad official)

  • Symbol: ADP1051ACPZ-R7
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
  • 3D model: LFCSP-24(4x4) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (108 pp, sha256 09eef5200e80f377, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF