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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

ADF4159CCPZ-RL7

Analog Devices · Clock Generators, PLLs, Frequency Synthesizers · LFCSP-24(4x4)

ADF4159CCPZ-RL7 from Analog Devices, in a LFCSP-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CPGND	power_in	Charge pump ground return that provides the ground reference path for the charge pump circuit.
2	AGND	power_in	Analog ground reference for the RF and analog signal processing circuitry.
3	AGND	power_in	Analog ground reference for the RF and analog signal processing circuitry.
4	RFINB	input	Complementary RF prescaler input requiring a 100 pF bypass capacitor to ground plane.
5	RFINA	input	AC-coupled RF prescaler input accepting 0.5 to 13 GHz signals at −10 to 0 dBm with minimum 400 V/µs slew rate.
6	AVDD	power_in	Positive 2.7 to 3.45 V analog power supply for RF section with decoupling capacitors required close to pin.
7	AVDD	power_in	Positive 2.7 to 3.45 V analog power supply for RF section with decoupling capacitors required close to pin.
8	AVDD	power_in	Positive 2.7 to 3.45 V analog power supply for RF section with decoupling capacitors required close to pin.
9	REFIN	input	Reference input accepting 10 to 260 MHz CMOS signal at −5 to +9 dBm with 100 kΩ input impedance.
10	DGND	power_in	Digital ground providing reference for logic and digital signal processing circuitry.
11	SDGND	power_in	Sigma-delta modulator ground providing return path for the Σ-Δ fractional interpolator circuit.
12	TXDATA	input	Transmit data input for FSK and PSK modulation control and ramp step triggering signals.
13	CE	input	Active-low chip enable input that powers down device and places charge pump into three-state mode.
14	CLK	input	Serial clock input for shifting 32-bit data words into the input shift register on rising clock edges.
15	DATA	input	Serial data input receiving MSB-first data with control bits in three LSBs at high impedance.
16	LE	input	Load enable input that latches 32-bit word from shift register into target register on rising edge.
17	MUXOUT	tri_state	Three-state multiplexer output providing access to internal signals including lock detect, divider outputs, and frequency readback.
18	SDVDD	power_in	Positive 1.8 V power supply for Σ-Δ modulator with decoupling capacitors required close to pin.
19	DVDD	power_in	Positive 1.62 to 1.98 V digital power supply for logic circuits with decoupling capacitors required close to pin.
20	SW1	passive	Fast lock mode switch pin that is shorted to ground to modify loop filter resistance during wideband lock operation.
21	SW2	passive	Fast lock mode switch pin that is connected to charge pump output for loop stabilization during wideband lock operation.
22	VP	power_in	Charge pump power supply accepting 2.7 to 3.45 V with requirement that VP ≥ AVDD.
23	RSET	passive	External resistor connection to ground for setting maximum charge pump current per ICP_MAX = 24.48 mA / RSET(kΩ).
24	CP	output	Charge pump output providing ±0.31 to 5.0 mA programmable current to external loop filter and VCO.
25	EPAD	power_in	Exposed thermal and electrical ground pad that must be soldered to AGND for proper heat dissipation.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	LFCSP-24(4x4)
Category	Clock/Timing
Pins	25

CAD (KiCad official)

Symbol: ADF4159CCPZ-RL7
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
3D model: LFCSP-24(4x4) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (36 pp, sha256 27a0d36b221191dc, retrieved 2026-09-17, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF