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Contents

README

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ADF41020BCPZ

Analog Devices · Clock Generators, PLLs, Frequency Synthesizers · LFCSP-20(4x4)

ADF41020BCPZ from Analog Devices, in a LFCSP-20(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground pin. Connect to system ground.
2 GND power_in Ground pin. Connect to system ground.
3 GND power_in Ground pin. Connect to system ground.
4 RFIN input RF prescaler input. AC-coupled internally (3 pF series cap with 50 Ω termination). Accepts 4.0 GHz to 18.0 GHz with input sensitivity −10 dBm to +10 dBm.
5 GND power_in Ground pin. Connect to system ground.
6 AVDD power_in Analog power supply for the fixed divide-by-4 prescaler. 2.85 V to 3.15 V. AVDD must equal DVDD. Decoupling capacitors should be placed as close as possible to this pin.
7 AVDD power_in Analog power supply. 2.85 V to 3.15 V. AVDD must equal DVDD. Decoupling capacitors should be placed as close as possible to this pin.
8 REFIN input Reference input. CMOS input with a nominal threshold of DVDD/2 and equivalent DC input resistance of ~100 kΩ. Can be driven by TTL or CMOS crystal oscillator or AC-coupled. REFIN frequency range 10 MHz to 400 MHz.
11 CE input Chip enable. A logic low powers down the device and puts the charge pump into three-state. Depending on the state of PD1, this pin can also enable power-up of the device.
12 CLK input Serial clock input for the 3-wire serial interface. Data is clocked into the 24-bit shift register on the rising edge of CLK. High-impedance CMOS input.
13 DATA input Serial data input. MSB first, with the two LSBs used as control bits selecting the destination latch. High-impedance CMOS input.
14 LE input Load enable. CMOS input. When LE goes high, data stored in the shift register is loaded into one of four latches selected by the control bits.
15 MUXOUT output Multiplexed output allowing external access to lock detect, and to a scaled version of the RF or reference frequency.
16 DVDD power_in Digital power supply. 2.85 V to 3.15 V. DVDD must equal AVDD. Decoupling capacitors should be placed as close as possible to this pin.
17 DVDD power_in Digital power supply. 2.85 V to 3.15 V. DVDD must equal AVDD. Decoupling capacitors should be placed as close as possible to this pin.
18 VP power_in Charge pump power supply. Should be greater than or equal to VDD. In systems where VDD = 3 V, VP can be up to 5.5 V.
19 RSET passive Charge-pump current setting resistor. A resistor between RSET and GND sets the maximum charge pump output current: ICP_MAX = 25.5 / RSET. Nominal RSET = 5.1 kΩ gives ICP_MAX = 5.0 mA. Pin nominal potential is 0.66 V.
20 CP output Charge pump output. When enabled, provides ±ICP to an external loop filter, which in turn drives the external VCO.
9 GND power_in Ground pin. Connect to system ground.
10 GND power_in Ground pin. Connect to system ground.
EP EPAD power_in Exposed thermal pad on the underside of the LFCSP package. Must be connected to GND for proper electrical and thermal performance.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-20(4x4)
Category Clock/Timing
Pins 21

Ordering variants

Same part, different packaging or reel option.

  • ADF41020BCPZ
  • ADF41020BCPZ-RL7

CAD (KiCad official)

  • Symbol: ADF41020BCPZ
  • Footprint: Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
  • 3D model: LFCSP-20(4x4) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (16 pp, sha256 4df286930020b6ba, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF