component

ADBMS1818ASWAZ-RL

Public Unreviewed

by Ray

Analog Devices Battery Management, LQFP-64-EP(10x10). Datasheet-verified pinout, KiCad symbol/footprint/3D.

componentpower management (pmic)adbms1818aswaz-rl
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads on click. Unloads when scrolled away or the tab is hidden.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads when scrolled away or the tab is hidden.

PCB Footprint

Open full view ↗
Loads on click. Unloads when scrolled away or the tab is hidden.

Datasheet

Open in new tab ↗
Loads on click. Unloads when scrolled away or the tab is hidden.
Download PDF
Contents

README

markdown

ADBMS1818ASWAZ-RL

Analog Devices · Battery Management · LQFP-64-EP(10x10)

ADBMS1818ASWAZ-RL from Analog Devices, in a LQFP-64-EP(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 V+ power_in Positive supply pin. Powered from the battery stack; typical 59.4 V for 18 cells, absolute maximum higher per datasheet.
2 C18 input Cell 18 top input to the ADC. Input range C(n-1) to C(n-1)+5 V.
3 S18 output Cell 18 balance discharge output. Internal N-channel MOSFET connects between S(n) and C(n-1) for passive balancing (up to 200 mA).
4 C17 input Cell 17 input to the ADC.
5 S17 output Cell 17 balance discharge output.
6 C16 input Cell 16 input to the ADC.
7 S16 output Cell 16 balance discharge output.
8 C15 input Cell 15 input to the ADC.
9 S15 output Cell 15 balance discharge output.
10 C14 input Cell 14 input to the ADC.
11 S14 output Cell 14 balance discharge output.
12 C13 input Cell 13 input to the ADC.
13 S13 output Cell 13 balance discharge output.
14 C12 input Cell 12 input to the ADC.
15 S12 output Cell 12 balance discharge output.
16 C11 input Cell 11 input to the ADC.
17 S11 output Cell 11 balance discharge output.
18 C10 input Cell 10 input to the ADC.
19 S10 output Cell 10 balance discharge output.
20 C9 input Cell 9 input to the ADC.
21 S9 output Cell 9 balance discharge output.
22 C8 input Cell 8 input to the ADC.
23 S8 output Cell 8 balance discharge output.
24 C7 input Cell 7 input to the ADC.
25 S7 output Cell 7 balance discharge output.
26 C6 input Cell 6 input to the ADC.
27 S6 output Cell 6 balance discharge output.
28 C5 input Cell 5 input to the ADC.
29 S5 output Cell 5 balance discharge output.
30 C4 input Cell 4 input to the ADC.
31 S4 output Cell 4 balance discharge output.
32 C3 input Cell 3 input to the ADC.
33 S3 output Cell 3 balance discharge output.
34 C2 input Cell 2 input to the ADC.
35 S2 output Cell 2 balance discharge output.
36 C1 input Cell 1 input to the ADC.
37 S1 output Cell 1 balance discharge output.
38 C0 input Cell 0 (bottom cell reference) input to the ADC. Input range 0 V to 1 V relative to V-.
39 GPIO1 bidirectional General purpose I/O. Digital in/out or analog input (0 V to 5 V measurement range).
40 GPIO2 bidirectional General purpose I/O. Digital in/out or analog input. Serves as SDA when GPIOs are configured as I2C master.
41 GPIO3 bidirectional General purpose I/O. Digital in/out or analog input. Serves as SPI CSB when GPIOs are configured as SPI master.
42 GPIO4 bidirectional General purpose I/O. Digital in/out or analog input. Serves as I2C SCL or SPI SDI when GPIOs are configured as I2C/SPI master.
43 GPIO5 bidirectional General purpose I/O. Digital in/out or analog input. Serves as SPI SCK when GPIOs are configured as SPI master.
44 GPIO6 bidirectional General purpose I/O. Digital in/out or analog input.
45 GPIO7 bidirectional General purpose I/O. Digital in/out or analog input.
46 GPIO8 bidirectional General purpose I/O. Digital in/out or analog input.
47 GPIO9 bidirectional General purpose I/O. Digital in/out or analog input.
48 VREG power_in 5 V regulator input/decoupling. Bypass with an external 1 uF capacitor.
49 DRIVE output Base drive for external NPN pass transistor that generates VREG. Connect the transistor collector to V+ and its emitter to VREG.
50 VREF2 power_out Buffered 2nd reference voltage (approx 3 V) for driving up to 10 kOhm thermistors. Bypass with a 1 uF capacitor.
51 VREF1 power_out ADC reference voltage (approx 3.15 V). Bypass with a 1 uF capacitor. No DC loads allowed.
52 DTEN input Discharge timer enable. Connect DTEN to VREG to enable the discharge timer; tie to V- to disable.
53 SDO/NC tri_state Port A pin. When ISOMD=V-: SDO, 4-wire SPI serial data out (open-drain NMOS, requires 5 kOhm pull-up). When ISOMD=VREG: NC (isoSPI mode).
54 SDI/NC input Port A pin. When ISOMD=V-: SDI, 4-wire SPI serial data in. When ISOMD=VREG: NC (isoSPI mode).
55 ISOMD input Serial interface mode select. Tie to VREG to configure pins 53/54/61/62 for 2-wire isoSPI (Port A). Tie to V- to configure them for 4-wire SPI.
56 WDT output Watchdog timer output. Open-drain NMOS. May be left floating or pulled up with a 1 MOhm resistor to VREG. Goes high impedance when a valid command is received within 2 s.
57 IBIAS passive Isolated interface current bias. Tie IBIAS to V- through a resistor divider to set the interface output current level; the pin sits at 2 V when isoSPI is enabled and IPA/IMA/IPB/IMB drive currents are 20x the IBIAS current.
58 ICMP passive Isolated interface comparator voltage threshold set. Tie ICMP to the resistor divider between IBIAS and V- to set the isoSPI receiver comparator threshold (half the ICMP voltage).
59 V- power_in Negative supply pin. Must be shorted externally to pin 60 and the exposed pad.
60 V- power_in Negative supply pin. Must be shorted externally to pin 59 and the exposed pad.
61 IPA/SCK bidirectional Port A pin. When ISOMD=VREG: IPA, isoSPI Port A positive differential I/O. When ISOMD=V-: SCK, 4-wire SPI clock input.
62 IMA/CSB bidirectional Port A pin. When ISOMD=VREG: IMA, isoSPI Port A negative differential I/O. When ISOMD=V-: CSB, 4-wire SPI active-low chip select input.
63 IMB bidirectional Isolated 2-wire serial interface Port B, negative differential I/O. Used for daisy-chain isoSPI communication regardless of ISOMD setting.
64 IPB bidirectional Isolated 2-wire serial interface Port B, positive differential I/O. Used for daisy-chain isoSPI communication regardless of ISOMD setting.
65 EPAD power_in Exposed thermal pad, electrically V-. Must be soldered to the PCB and shorted to pins 59 and 60.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LQFP-64-EP(10x10)
Category Power Management (PMIC)
Pins 65

Ordering variants

Same part, different packaging or reel option.

  • ADBMS1818ASWAZ-RL

CAD (KiCad official)

  • Symbol: ADBMS1818ASWAZ-RL
  • Footprint: Package_QFP:LQFP-64-1EP_10x10mm_P0.5mm_EP6.5x6.5mm
  • 3D model: LQFP-64-EP(10x10) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (89 pp, sha256 f1ad8af4c41d6bce, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF