AD9910BSVZ-REEL from Analog Devices, in a TQFP-100-EP(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	NC	unconnected	Not Connected. Allow device pin to float.
2	PLL_LOOP_FILTER	passive	PLL Loop Filter Compensation Pin. External RC network sets loop dynamics of the REFCLK multiplier PLL.
3	AVDD_1V8	power_in	Analog Core VDD, 1.8 V analog supply.
4	AGND	power_in	Analog Ground.
5	AGND	power_in	Analog Ground.
6	AVDD_1V8	power_in	Analog Core VDD, 1.8 V analog supply.
7	SYNC_IN+	input	LVDS synchronization signal input (rising edge active). Positive leg of differential sync input from an external master to synchronize internal subclocks.
8	SYNC_IN-	input	LVDS synchronization signal input. Negative leg of differential sync input from an external master to synchronize internal subclocks.
9	SYNC_OUT+	output	LVDS synchronization signal output (rising edge active). Positive leg of differential sync output used to synchronize external slave devices.
10	SYNC_OUT-	output	LVDS synchronization signal output. Negative leg of differential sync output used to synchronize external slave devices.
11	DVDD_IO_3V3	power_in	Digital Input/Output VDD, 3.3 V digital supply.
12	SYNC_SMP_ERR	output	Synchronization Sample Error, digital output (active high). A high indicates the AD9910 did not receive a valid sync signal on SYNC_IN+/SYNC_IN-.
13	DGND	power_in	Digital Ground.
14	MASTER_RESET	input	Master Reset, digital input (active high). Clears all memory elements and sets registers to default values.
15	DVDD_IO_3V3	power_in	Digital Input/Output VDD, 3.3 V digital supply.
16	DGND	power_in	Digital Ground.
17	DVDD_1V8	power_in	Digital Core VDD, 1.8 V digital supply.
18	EXT_PWR_DWN	input	External Power-Down, digital input (active high). Initiates the currently programmed power-down mode. Tie to ground if unused.
19	PLL_LOCK	output	Clock Multiplier PLL Lock, digital output (active high). A high indicates the REFCLK multiplier PLL has acquired lock.
20	NC	unconnected	Not Connected. Allow device pin to float.
21	DVDD_IO_3V3	power_in	Digital Input/Output VDD, 3.3 V digital supply.
22	DGND	power_in	Digital Ground.
23	DVDD_1V8	power_in	Digital Core VDD, 1.8 V digital supply.
24	RAM_SWP_OVR	output	RAM Sweep Over, digital output (active high). A high indicates that the RAM sweep profile has completed.
25	D15	input	Parallel Input Bus bit 15 (active high). Modulation data for the parallel data port.
26	D14	input	Parallel Input Bus bit 14 (active high).
27	D13	input	Parallel Input Bus bit 13 (active high).
28	DVDD_IO_3V3	power_in	Digital Input/Output VDD, 3.3 V digital supply.
29	DGND	power_in	Digital Ground.
30	DVDD_1V8	power_in	Digital Core VDD, 1.8 V digital supply.
31	D12	input	Parallel Input Bus bit 12 (active high).
32	D11	input	Parallel Input Bus bit 11 (active high).
33	D10	input	Parallel Input Bus bit 10 (active high).
34	D9	input	Parallel Input Bus bit 9 (active high).
35	D8	input	Parallel Input Bus bit 8 (active high).
36	D7	input	Parallel Input Bus bit 7 (active high).
37	D6	input	Parallel Input Bus bit 6 (active high).
38	D5	input	Parallel Input Bus bit 5 (active high).
39	D4	input	Parallel Input Bus bit 4 (active high).
40	PDCLK	output	Parallel Data Clock, digital output. Provides a timing signal for aligning data at the parallel inputs.
41	TxENABLE	input	Transmit Enable, digital input (active high). In burst mode a high indicates new data for transmission; in continuous mode this pin remains high.
42	D3	input	Parallel Input Bus bit 3 (active high).
43	D2	input	Parallel Input Bus bit 2 (active high).
44	D1	input	Parallel Input Bus bit 1 (active high).
45	DVDD_IO_3V3	power_in	Digital Input/Output VDD, 3.3 V digital supply.
46	DGND	power_in	Digital Ground.
47	DVDD_1V8	power_in	Digital Core VDD, 1.8 V digital supply.
48	D0	input	Parallel Input Bus bit 0 (active high).
49	F1	input	Modulation Format Pin F[1]. Digital input that determines the parallel-port modulation format.
50	F0	input	Modulation Format Pin F[0]. Digital input that determines the parallel-port modulation format.
51	DGND	power_in	Digital Ground.
52	PROFILE2	input	Profile Select Pin bit 2 (active high). Selects one of eight phase/frequency profiles for the DDS.
53	PROFILE1	input	Profile Select Pin bit 1 (active high). Selects one of eight phase/frequency profiles for the DDS.
54	PROFILE0	input	Profile Select Pin bit 0 (active high). Selects one of eight phase/frequency profiles for the DDS.
55	SYNC_CLK	output	Output Clock Divided-By-Four. Digital output clock; many digital inputs (I/O_UPDATE, PROFILE[2:0], etc.) must be set up on the rising edge of this signal.
56	DVDD_IO_3V3	power_in	Digital Input/Output VDD, 3.3 V digital supply.
57	DVDD_1V8	power_in	Digital Core VDD, 1.8 V digital supply.
58	DGND	power_in	Digital Ground.
59	I/O_UPDATE	bidirectional	Input/Output Update, digital I/O (active high). A high transfers the contents of the I/O buffers to the corresponding internal registers.
60	OSK	input	Output Shift Keying, digital input (active high). Controls the OSK function; in manual mode toggles amplitude between zero and programmed scale, in automatic mode sweeps amplitude down/up.
61	DROVER	output	Digital Ramp Over, digital output (active high). Switches high whenever the digital ramp generator reaches its programmed upper or lower limit.
62	DRCTL	input	Digital Ramp Control, digital input (active high). Controls the slope polarity of the digital ramp generator. Tie low if DRG unused.
63	DRHOLD	input	Digital Ramp Hold, digital input (active high). Stalls the digital ramp generator in its present state. Tie low if DRG unused.
64	DVDD_1V8	power_in	Digital Core VDD, 1.8 V digital supply.
65	DGND	power_in	Digital Ground.
66	DVDD_IO_3V3	power_in	Digital Input/Output VDD, 3.3 V digital supply.
67	SDIO	bidirectional	Serial Data Input/Output (active high). Bidirectional serial data line by default; unidirectional (input only) when configured.
68	SDO	output	Serial Data Output, digital output (active high). Only active in unidirectional serial data mode; leave floating in bidirectional mode.
69	SCLK	input	Serial Data Clock. Rising edge on write, falling edge on read. Provides the serial data clock for the control data path.
70	CS	input	Chip Select, digital input (active low). Low enables the AD9910 to detect serial clock rising/falling edges on the serial data pins; high causes it to ignore input.
71	I/O_RESET	input	Input/Output Reset, digital input (active high). Used when a serial I/O communication cycle fails. Tie to ground when not used.
72	NC	unconnected	Not Connected. Allow device pin to float.
73	AGND	power_in	Analog Ground.
74	AVDD_3V3	power_in	Analog DAC VDD, 3.3 V analog supply.
75	AVDD_3V3	power_in	Analog DAC VDD, 3.3 V analog supply.
76	AVDD_3V3	power_in	Analog DAC VDD, 3.3 V analog supply.
77	AVDD_3V3	power_in	Analog DAC VDD, 3.3 V analog supply.
78	AGND	power_in	Analog Ground.
79	AGND	power_in	Analog Ground.
80	IOUTB	output	Open-Drain DAC Complementary Output Source, analog current-mode output. Connect through a 50 ohm resistor to AGND.
81	IOUT	output	Open-Drain DAC Output Source, analog current-mode output. Connect through a 50 ohm resistor to AGND.
82	AGND	power_in	Analog Ground.
83	AVDD_3V3	power_in	Analog DAC VDD, 3.3 V analog supply.
84	DAC_RSET	passive	Analog Reference Pin. Programs the DAC output full-scale reference current. Attach a 10 kohm resistor to AGND.
85	AGND	power_in	Analog Ground.
86	NC	unconnected	Not Connected. Allow device pin to float.
87	NC	unconnected	Not Connected. Allow device pin to float.
88	AGND	power_in	Analog Ground.
89	AVDD_1V8	power_in	Analog Core VDD, 1.8 V analog supply.
90	REF_CLK	input	Reference Clock Input, analog input. Can be driven by an external oscillator or connected to a crystal when the internal oscillator is engaged.
91	REF_CLKB	input	Reference Clock Input (complementary), analog input. Negative leg of the differential reference clock.
92	AVDD_1V8	power_in	Analog Core VDD, 1.8 V analog supply.
93	NC	unconnected	Not Connected. Allow device pin to float.
94	REFCLK_OUT	output	Crystal Output, analog output. Used with the internal oscillator when driven from a crystal (see REF_CLK Overview).
95	XTAL_SEL	input	Crystal Select (1.8 V logic), analog input (active high). Driving high enables the internal oscillator to be used with a crystal resonator. Tie to AGND if unused.
96	AGND	power_in	Analog Ground.
97	NC	unconnected	Not Connected. Allow device pin to float.
98	NC	unconnected	Not Connected. Allow device pin to float.
99	NC	unconnected	Not Connected. Allow device pin to float.
100	NC	unconnected	Not Connected. Allow device pin to float.
EPAD	EPAD	power_in	Exposed Paddle. Must be soldered to ground for proper thermal and electrical performance.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	TQFP-100-EP(14x14)
Category	Data Acquisition
Pins	101

Ordering variants

Same part, different packaging or reel option.

AD9910BSVZ-REEL

CAD (KiCad official)

Symbol: AD9910BSVZ-REEL
Footprint: Package_QFP:TQFP-100-1EP_14x14mm_P0.5mm_EP5x5mm
3D model: TQFP-100-EP(14x14) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (64 pp, sha256 e84adc31ccf0b2ff, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF